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    Integrated circuit with identification signal writing circuitry distributed on multiple metal layers
    2.
    发明公开
    Integrated circuit with identification signal writing circuitry distributed on multiple metal layers 审中-公开
    包括：在多个金属层的集成电路分布式布线用于写入的识别信号

    公开(公告)号：EP1100125A1

    公开(公告)日：2001-05-16

    申请号：EP99830699.7

    申请日：1999-11-10

    Applicant: STMicroelectronics S.r.l.

    Inventor： Vai, Gianfranco ,  Savo, Pierandrea

    IPC: H01L23/544 ,  G06F11/00 ,  G11C17/10

    CPC classification number: G11C17/10 ,  G06F11/006 ,  H01L23/544 ,  H01L2223/5444 ,  H01L2223/54473 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Integrated device (100) comprising a plurality of conducting layers (115a-115c), each having a first (120ga-120gc) and a second (120va-120vc) power supply contact for providing, respectively, a first and a second binary value, and means for supplying at least one identification bit of a version of the integrated device (100); the integrated device (100) includes, for each identification bit, parity check means (135abi, 135bci) having a plurality of input terminals whose number is equal to the number of conducting layers (115a-115c), and an output terminal, each input terminal being connected to one contact selected from the first (120ga-120gc) and the second (120va-120vc) power supply contacts of a corresponding one of the conducting layers (115a-115c), and the output terminal supplying the corresponding identification bit.

    Abstract translation: 集成器件（100）包括导电层（115A-115C）的复数，每个都具有第一（120ga-120gc）和用于提供第二（120VA-120vc）供电接触件，分别为第一和第二二进制值， 和装置，用于提供一个版本的集成设备（100）中的至少一个识别位; 集成器件（100）包括，对于每个识别位，奇偶校验手段（135abi，135bci），其具有输入端子，其数量等于导电层（115A-115C）的数量，和输出端子的复数，每个输入 端子被连接到从第一（120ga-120gc）选择的一个接触，并且相应的所述导电层中的一个（115A-115C）的第二个（120VA-120vc）电源触点，和输出端供给对应的识别位。

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