公开(公告)号：EP0794609A1

公开(公告)日：1997-09-10

申请号：EP96830103.6

申请日：1996-03-08

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l. ,  CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Bruccoleri, Melchiorre ,  Cosentino, Gaetano ,  Demicheli, Marco ,  Pisati, Valerio

IPC: H03B1/00 ,  H03L7/099

CPC classification number: H03L7/0805 ,  H03L7/099

Abstract: The system described comprises various circuit units (10, 11, 12) each having a capacitor (C0, C1, C2) and charging means (G0, G1, G2) for defining a quantity depending upon the ratio (I/C) between the charging current and the capacitance of the capacitors.
In order to compensate automatically for deviations of the actual capacitances from the nominal capacitances due to fluctuations in the parameters of the integrated-circuit manufacturing process, the system has a phase-locked loop (PLL) which uses one (10) of the circuit units as an adjustable oscillator, and current transducer means (17) which regulate the charging currents of the capacitors (C1, C2) of the circuit units (11, 12) in dependence on the regulated charging current of the capacitor (C0) of the oscillator (10) or the error current of the PLL loop.

Abstract translation: 所描述的系统包括各种电路单元（10，11，12），每个具有一个电容器（C0，C1，C2）和用于在所述之间的比率（I / C）定义的量DEPENDING充电装置（G0，G1，G2） 充电电流和电容器的电容。 为了由于在集成电路制造工艺的参数的波动自动为从标称电容的实际电容的偏差进行补偿，该系统具有电路单元的锁相环（PLL），其使用（10）之一 作为可调振荡器，和电流传感器装置（17）从而调节电容器的电路单元的充电电流（C1，C2）（11，12）在根据所述振荡器的电容器的调节充电电流（C0） （10）或者PLL环路的误差电流。

公开(公告)号：EP0810723A1

公开(公告)日：1997-12-03

申请号：EP96830311.5

申请日：1996-05-31

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l. ,  CO.RI.M.ME.

Inventor： Pisati, Valerio ,  Alini, Roberto ,  Cosentino, Gaetano ,  Vai, Gianfranco

IPC: H03H1/00 ,  H03F3/45 ,  H03F3/72

CPC classification number: H03F3/72 ,  H03F3/45286 ,  H03F2203/45302 ,  H03F2203/45304 ,  H03F2203/45371 ,  H03F2203/45396 ,  H03F2203/45506

Abstract: A BiCMOS Transconductor differential stage (10) for high frequency filters comprises an input circuit portion having signal inputs (IN+,IN-) and comprising a pair of MOS transistors (M1,M2) having their respective gate terminals (G1,G2) corresponding to the signal inputs as well as an output circuit portion having signal outputs (OUT-,OUT+) and comprising a pair of two-pole transistors (Q1,Q2) connected together with a common base in a circuit node (B) and inserted between inputs (IN+,IN-) and outputs (OUT-,OUT+) in cascode configuration. The stage (10) in accordance with the present invention calls for a switching device (3) associated with at least one of said added two-pole transistors (Q1,Q2) to change the connections between the parasite capacitors present in the transconductor stage. The switching device (3) also comprises at least one added two-pole transistor (Q1x, Q2x) connected in a removable manner in parallel with the corresponding two-pole cascode transistor (Q1,Q2).
In a variant embodiment there are also provided respective added MOS transistors (M1x,M2x) connected in parallel with the MOS transistors (M1,M2) of the input portion to change the ratio W:L of each of the input transistors (M1,M2).

Abstract translation: 一种用于高频滤波器的BiCMOS跨导差分级（10）包括具有信号输入端（IN +，IN-）并包括一对MOS晶体管（M1，M2）的输入电路部分，所述一对MOS晶体管的各自的栅极端子（G1，G2） 信号输入端以及具有信号输出端（OUT-，OUT +）的输出电路部分，并且包括在电路节点（B）中用公共基极连接在一起的一对双极晶体管（Q1，Q2），并插入在输入端 （IN +，IN-）和输出（OUT-，OUT +）级联配置。 根据本发明的级（10）需要与所述增加的双极晶体管（Q1，Q2）中的至少一个相关联的开关器件（3）改变跨导级中存在的寄生电容器之间的连接。 开关器件（3）还包括至少一个与对应的双极共源共栅晶体管（Q1，Q2）并联连接的增加的双极晶体管（Q1x，Q2x）。 在变型实施例中，还提供了与输入部分的MOS晶体管（M1，M2）并联连接的相应增加的MOS晶体管（M1x，M2x），以改变每个输入晶体管（M1，M2）的比率W:L ）。

公开(公告)号：EP0786858A1

公开(公告)日：1997-07-30

申请号：EP96830035.0

申请日：1996-01-26

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l. ,  CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Alini, Roberto ,  Bruccoleri, Melchiorre ,  Cosentino, Gaetano ,  Pisati, Valerio

IPC: H03F1/00 ,  H03F3/30

CPC classification number: H03F3/3077

Abstract: The amplifier described has an output stage constituted by an npn transistor (Q1) and a pnp transistor (Q2) in a push-pull arrangement, and a driver stage. The latter comprises a current-mirror circuit having, in its input branch, a pnp transistor (Q3) in series with a first constant-current generator (G1) and, in its output branch, an npn transistor (Q4), and two complementary transistors (Q5 and Q6) of which the collectors are connected together to the output terminal (OUT) and the bases are connected together to the input terminal (IN) of the amplifier. The emitter of the pnp transistor (Q5) of the driver stage is connected to the positive terminal (vdd) of the supply by means of a second constant-current generator (G2) and to the base of the npn transistor (Q1) of the output stage, and the emitter of the npn transistor (Q6) of the driver stage is connected to the negative terminal (gnd) of the supply by means of the npn transistor (Q4) of the output branch of the current-mirror circuit and to the base of the pnp transistor (Q2) of the output stage.
The amplifier has a very low or zero offset ( Vos = Vout-Vin ).

Abstract translation: 所描述的放大器具有由推挽装置中的npn晶体管（Q1）和pnp晶体管（Q2）和驱动器级构成的输出级。 后者包括电流镜电路，其在其输入支路中具有与第一恒定电流发生器（G1）串联的pnp晶体管（Q3），并且在其输出支路中具有npn晶体管（Q4）和两个互补的 集电极一起连接到输出端（OUT）的晶体管（Q5和Q6）和基极连接在放大器的输入端（IN）上。 驱动级的pnp晶体管（Q5）的发射极通过第二恒流发生器（G2）连接到电源的正端子（vdd），并连接到电源的npn晶体管（Q1）的基极 输出级，并且驱动级的npn晶体管（Q6）的发射极通过电流镜电路的输出支路的npn晶体管（Q4）连接到电源的负极（gnd），并且 输出级的pnp晶体管（Q2）的基极。 放大器具有非常低或零偏移（Vos = Vout-Vin）。

公开(公告)号：EP0711041A1

公开(公告)日：1996-05-08

申请号：EP94830523.0

申请日：1994-11-03

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Gadducci, Paolo ,  Demicheli, Marco ,  Pisati, Valerio ,  Alini, Roberto

IPC: H03L7/14 ,  H03L7/089

CPC classification number: H03L7/089 ,  H03L7/148

Abstract: A phase-locked circuit for regulating the frequency of a controllable oscillator (ICO2) at a preset value is described. It comprises a reference oscillator (ICO1) which generates a signal at the preset frequency, a phase detector (10) which receives the signals from the two oscillators and produces a phase error signal, and processing circuit means which can apply a signal which is a function of the magnitude and sign of the phase error at the regulating terminal of the controllable oscillator (ICO2).
In order to enable the feedback loop to open for an indefinite period after a phase-locking while still maintain the frequency at the preset value, the processing circuit means comprise a counter (CNT) which numerically measures the phase error and a digital-to-analogue convertor (DAC) which produces an input signal corresponding to the numerical measurement.

Abstract translation: 描述了用于将可控振荡器（ICO2）的频率调节到预设值的锁相电路。 它包括产生预置频率信号的基准振荡器（ICO1），接收来自两个振荡器的信号并产生相位误差信号的相位检测器（10），以及处理电路装置，其能够将作为 在可控振荡器（ICO2）的调节端处的相位误差的幅度和符号的函数。 为了使得反馈回路在锁相之后无限期地打开，同时仍将频率保持在预设值，处理电路装置包括计数器（CNT），该计数器在数值上测量相位误差，并且数字 - 模拟转换器（DAC），它产生对应于数字测量的输入信号。

公开(公告)号：EP0584437A1

公开(公告)日：1994-03-02

申请号：EP92830456.7

申请日：1992-08-26

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Castello, Rinaldo ,  Alini, Roberto ,  Rezzi, Francesco ,  Pisati, Valerio

IPC: H03F1/32 ,  H03F3/45

CPC classification number: H03F1/3211 ,  H03F3/45076 ,  H03F3/45282

Abstract: A transconductor stage (1) for high-frequency filters (5), of a type which comprises an input circuit portion having signal inputs (A,B) and an output circuit portion, incorporates a pair of field-effect transistors (M1,M2) having respective gate (G1,G2) and source (S1,S2) terminals in common, and has the output portion formed of a pair of bipolar transistors (Q1,Q2) connected to the aforesaid field-effect transistors.

Abstract translation: 一种用于高频滤波器（5）的跨导级（1），其包括具有信号输入（A，B）和输出电路部分的输入电路部分的类型，包括一对场效应晶体管（M1，M2 ）具有相同的栅极（G1，G2）和源极（S1，S2）端子，并且具有由连接到上述场效应晶体管的一对双极晶体管（Q1，Q2）形成的输出部分。

公开(公告)号：EP0751457A1

公开(公告)日：1997-01-02

申请号：EP95830278.8

申请日：1995-06-30

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Gadducci, Paolo ,  Moloney, David ,  Brianti, Francesco ,  Pisati, Valerio

IPC: G06F7/02

CPC classification number: G06F7/026

Abstract: The invention relates to a basic cell (11) for comparing a first and a second digital signal (A, B), of the type having at least a first and a second input (I1, I2) and a first and a second output (O3, O4) and comprising at least one logic gate (14) receiving digital signals (A, B) at a first and a second signal input (IS1, IS2), and which comprises at least a first and a second controlled switch (P1, P2) inserted in parallel with each other between the output terminal of the logic gate (14) and the second output (O4) from the cell (11), the first switch (P1) being also connected between the first input (I1) and the first output (O3) of the cell (11) and the second switch (P2) being also connected between the second input (I2) and the second output (O4) of the cell (11).
The invention also relates to a digital comparator (9) comprising a plurality of basic cells according to the invention.

Abstract translation: 本发明涉及的基本单元（11），用于比较第一和第二数字信号（A，B），其具有至少一个第一和一个第二输入（I1，I2）和第一和第二输出的类型的（ O3，O4）和包括至少一个逻辑门（14）在接收到数字信号（A，B）在第一和第二信号输入端（IS1，IS2），并且其包括至少一个第一和一个第二可控开关（P1 ，P2）插入到彼此平行的逻辑门（14）和从所述小区（11），第一开关（P1的第二输出端（O4）的输出端子之间），以便被连接在第一输入（I1之间） 并由此被连接在第二输入（I 2）和电池（11）的第二输出（O4）之间的单元（11）和所述第二开关（P2）的第一输出（O3）。 因此本发明涉及到一个数字比较器（9）包括gemäß发明基本单元的复数。

公开(公告)号：EP0729228A1

公开(公告)日：1996-08-28

申请号：EP95830049.3

申请日：1995-02-22

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Alini, Roberto ,  Brianti, Francesco ,  Pisati, Valerio ,  Demicheli, Marco

IPC: H03H1/00 ,  H03H11/04 ,  H03H15/00

CPC classification number: H03H15/00 ,  H03H11/0422

Abstract: An elementary cell structure for programmable time-continuous analog filters and in particular for the processing of analog signals in read/write operations on magnetic supports comprises an amplifier stage (3) provided with a pair of structurally identical transconductance half-cells (2,2') connected together in a common circuit node (X).
With a cascade of cells of this type is provided a time-continuous analog delay line which is used in a transverse time-continuous analog filter. This filter comprises a cascade of identical delay lines (LR) connected through multiplier nodes (5) to a final summation node (6).

Abstract translation: 用于可编程时间连续模拟滤波器的基本单元结构，特别是用于在磁性支撑上的读取/写入操作中处理模拟信号的放大器级（3）包括具有一对结构相同的跨导半电池（2,2 '）在公共电路节点（X）中连接在一起。 这种级联的这种类型的单元被提供用于横向时间连续的模拟滤波器的时间连续的模拟延迟线。 该滤波器包括通过乘法器节点（5）连接到最终求和节点（6）的相同延迟线（LR）的级联。

公开(公告)号：EP0743758A1

公开(公告)日：1996-11-20

申请号：EP95830197.0

申请日：1995-05-15

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Bruccoleri, Melchiorre ,  Demicheli, Marco ,  Patti, Giuseppe ,  Pisati, Valerio

IPC: H03M1/00 ,  G06J1/00 ,  H03M1/78

CPC classification number: H03M1/664 ,  G06J1/00 ,  H03M1/785

Abstract: A digital/analog quadratic converter (DACQ) composed by a pair of linear converters connected in cascade has a direct coupling of the output node of the first converter (DAC1) with a node of a R-2R type resistive network of the second converter (DAC2) corresponding to the LSB stage of the R-2R type resistive network. High impedance nodes, notably the input node of the second linear converter, are advantageously eliminated from the "current path" thus markedly reducing the problems of relatively long settling times of high impedance nodes (having intrinsically large parasitic capacitances associated therewith). The peculiar architecture of the quadratic converter provides also for a remarkable simplification of the circuit.

Abstract translation: 由串联的一对线性转换器组成的数字/模拟二次转换器（DACQ）具有第一转换器（DAC1）的输出节点与第二转换器的R-2R型电阻网络的节点的直接耦合（ DAC2）对应于R-2R型电阻网络的LSB级。 高阻抗节点，特别是第二线性转换器的输入节点，有利地从“电流路径”中消除，从而显着地减少了高阻抗节点（具有与其相关的本质上大的寄生电容）的较长建立时间的问题。 二次转换器的独特结构也为电路的显着简化提供了依据。

公开(公告)号：EP0696846A1

公开(公告)日：1996-02-14

申请号：EP94830401.9

申请日：1994-08-12

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Brianti, Francesco ,  Alini, Roberto ,  Pisati, Valerio ,  Gadducci, Paolo

IPC: H03H1/00 ,  H03H11/04

CPC classification number: H03H11/0433

Abstract: A high-pass filter in particular for high-frequency applications and of the type comprising at least one input terminal (IN) and at least one output terminal (OUT) between which is defined a transfer function (FdT) and is inserted a biquadratic cell (18) incorporating a series of transconductance stages (2, 3, 4, 5) comprises a generator circuit (29) of variable currents (i K1 , i K2 ) connected between a pair of stages (2, 3) of the biquadratic cell (18) and a voltage reference (GND). Said generator allows introduction of programmable zeroes in the transfer function (FdT) of the filter (20).

Abstract translation: 一种高通滤波器，特别是用于高频应用，并且包括至少一个输入端（IN）和至少一个输出端（OUT）的类型，其间被定义为传输函数（FdT），并且插入一个二次电池 包括一系列跨导级（2,3,4,5）的（18）包括连接在所述二次电池（18）的一对级（2,3）之间的可变电流（iK1，iK2）的发生器电路（29） ）和参考电压（GND）。 所述发生器允许在滤波器（20）的传递函数（FdT）中引入可编程零点。 $$

公开(公告)号：EP0695030A1

公开(公告)日：1996-01-31

申请号：EP94830390.4

申请日：1994-07-29

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Pisati, Valerio ,  Alini, Roberto ,  Castello, Rinaldo ,  Vai, Gianfranco

IPC: H03G1/00 ,  H03F1/08 ,  H03H11/04

CPC classification number: H03F3/45883 ,  H03F3/45286 ,  H03F3/45807 ,  H03F2203/45648 ,  H03G1/0023

Abstract: A controlled gain transconductor (20) which comprises a transconductance stage (3) having at least two input terminals (I1, I2) and at least two output terminals (O1, O2), an active load (4) connected to the output terminals of the transconductance stage and a control circuit (5) for the active load (4) conneccted between said output terminals (O1, O2) and the active load (4).
Also provided is a circuit portion (10) being a replica of the transconductance stage (3), the active load (4) and the control circuit (5). This replicated portion (10) has an output connected to the control circuit (5) of the transconductor (20) to provide a predetermined voltage value (Vc) required for adjusting the DC gain of the device.

Abstract translation: 一种受控增益跨导体（20），包括具有至少两个输入端（I1，I2）和至少两个输出端（O1，O2）的跨导级（3），连接到输出端 所述跨导级和用于所述输出端子（O1，O2）和所述有源负载（4）之间连接的有源负载（4）的控制电路（5）。 还提供了作为跨导级（3），有源负载（4）和控制电路（5）的复制品的电路部分（10）。 该复制部分（10）具有连接到跨导体（20）的控制电路（5）的输出端，以提供调节器件的直流增益所需的预定电压值（Vc）。 $$