公开(公告)号：US20230009791A1

公开(公告)日：2023-01-12

申请号：US17545442

申请日：2021-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yunseong LEE ,  Jinseong HEO ,  Taehwan MOON ,  Seunggeol NAM ,  Dukhyun CHOE

IPC: H01L29/51 ,  H01L27/11502 ,  H01L27/11585

Abstract: A layer structure including a dielectric layer, a method of manufacturing the layer structure, and an electronic device including the layer structure are disclosed. The layer structure including a lower layer, a dielectric layer, and an upper layer sequentially stacked. The dielectric layer includes sequentially stacked first, second, and third layers, wherein one of the first layer or the third layer is a ferroelectric, the other one is an antiferroelectric, and the second layer is an oxide layer. In one example, the dielectric layer may further include a fourth layer on the third layer.

公开(公告)号：US20220241884A1

公开(公告)日：2022-08-04

申请号：US17722746

申请日：2022-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinseong HEO ,  Yunseong LEE ,  Sanghyun JO

IPC: B23K3/08 ,  B23K3/06 ,  H01L23/00 ,  H01L27/11585 ,  H01L29/66

Abstract: Provided are a logic switching device and a method of manufacturing the same. The logic switching device may include a domain switching layer adjacent to a gate electrode. The domain switching layer may include a ferroelectric material region and an anti-ferroelectric material region. The domain switching layer may be a non-memory element. The logic switching device may include a channel, a source and a drain both connected to the channel, the gate electrode arranged to face the channel, and the domain switching layer provided between the channel and the gate electrode.

公开(公告)号：US20220173099A1

公开(公告)日：2022-06-02

申请号：US17491841

申请日：2021-10-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangwook KIM ,  Seunggeol NAM ,  Taehwan MOON ,  Kwanghee LEE ,  Jinseong HEO ,  Hagyoul BAE ,  Yunseong LEE

IPC: H01L27/092 ,  H01L27/11 ,  H01L29/24 ,  H01L29/51 ,  H01L29/78 ,  H01L29/786

Abstract: Provided is a semiconductor device including a first semiconductor transistor including a semiconductor channel layer, and a metal-oxide semiconductor channel layer, and having a structure in which a second semiconductor transistor is stacked on the top of the first semiconductor transistor. A gate stack of the second semiconductor transistor and the top of a gate stack of the first semiconductor transistor may overlap by greater than or equal to 90%. The first semiconductor transistor and the second semiconductor transistor may have a similar level of operation characteristics.

公开(公告)号：US20220140148A1

公开(公告)日：2022-05-05

申请号：US17515984

申请日：2021-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunggeol NAM ,  Jinseong HEO ,  Sangwook KIM ,  Hagyoul BAE ,  Taehwan MOON ,  Yunseong LEE

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/51

Abstract: Provided is a ferroelectric semiconductor device including a source and a drain having different polarities. The ferroelectric semiconductor may include a ferroelectric including zirconium oxide (ZrO2), hafnium oxide (HfO2), and/or hafnium-zirconium oxide (HfxZr1−xO, 0

公开(公告)号：US20220028872A1

公开(公告)日：2022-01-27

申请号：US17496299

申请日：2021-10-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinseong HEO ,  Yunseong LEE ,  Sanghyun JO

IPC: H01L27/1159 ,  H01L29/78 ,  H01L29/66 ,  G11C11/22 ,  H01L21/28

Abstract: Provided are an electronic device and a method of manufacturing the same. The electronic device may include a first device provided on a first region of a substrate; and a second device provided on a second region of the substrate, wherein the first device may include a first domain layer including a ferroelectric domain and a first gate electrode on the first domain layer, and the second device may include a second domain layer including a ferroelectric domain and a second gate electrode on the second domain layer. The first domain layer and the second domain layer may have different characteristics from each other at a polarization change according to an electric field. At the polarization change according to the electric field, the first domain layer may have substantially a non-hysteretic behavior characteristic and the second domain layer may have a hysteretic behavior characteristic.

公开(公告)号：US20210098595A1

公开(公告)日：2021-04-01

申请号：US16890231

申请日：2020-06-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yunseong LEE ,  Sangwook KIM ,  Sanghyun JO ,  Jinseong HEO ,  Hyangsook LEE

IPC: H01L29/51 ,  H01L29/78 ,  H01L21/02

Abstract: A ferroelectric thin-film structure includes at least one first atomic layer and at least one second atomic layer. The first atomic layer includes a first dielectric material that is based on an oxide, and the second atomic layer includes both the first dielectric material and a dopant that has a bandgap greater than a bandgap of the dielectric material.

公开(公告)号：US20190031906A1

公开(公告)日：2019-01-31

申请号：US15925034

申请日：2018-03-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangwon KIM ,  Minsu SEOL ,  Hyeonjin SHIN ,  Dongwook LEE ,  Yunseong LEE ,  Seongjun JEONG ,  Alum JUNG

IPC: C09D165/00 ,  C01B32/184 ,  G03F7/16 ,  G03F7/20 ,  G03F7/38 ,  G03F7/32 ,  H01L21/311 ,  H01L21/027

CPC classification number: C09D165/00 ,  B82Y30/00 ,  B82Y40/00 ,  C01B32/182 ,  C01B32/184 ,  C08G61/02 ,  C08G2261/3424 ,  G03F7/094 ,  G03F7/162 ,  G03F7/168 ,  G03F7/2004 ,  G03F7/322 ,  G03F7/38 ,  H01L21/0274 ,  H01L21/31138 ,  H01L21/31144 ,  Y10S977/734 ,  Y10S977/774 ,  Y10S977/842

Abstract: Provided are a method of preparing a graphene quantum dot, a graphene quantum dot prepared using the method, a hardmask composition including the graphene quantum dot, a method of forming a pattern using the hardmask composition, and a hardmask obtained from the hardmask composition. The method of preparing a graphene quantum dot includes reacting a graphene quantum dot composition and an including a polyaromatic hydrocarbon compound and an organic solvent at an atmospheric pressure and a temperature of about 250° C. The polyaromatic hydrocarbon compound may include at least four aromatic rings.

公开(公告)号：US20170229546A1

公开(公告)日：2017-08-10

申请号：US15494035

申请日：2017-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seongjun JEONG ,  Seongjun PARK ,  Yunseong LEE

IPC: H01L29/16 ,  H01L29/786 ,  H01L21/04 ,  H01L21/8234 ,  H01L21/02 ,  H01L29/06 ,  H01L27/088

CPC classification number: H01L29/1606 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02527 ,  H01L21/02603 ,  H01L21/042 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/467 ,  H01L21/823412 ,  H01L27/088 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/66037 ,  H01L29/66045 ,  H01L29/775 ,  H01L29/778 ,  H01L29/78696 ,  H01L51/0045 ,  Y10S977/755 ,  Y10S977/888

Abstract: Methods of forming a graphene nanopattern, graphene-containing devices, and methods of manufacturing the graphene-containing devices are provided. A method of forming the graphene nanopattern may include forming a graphene layer on a substrate, forming a block copolymer layer on the graphene layer and a region of the substrate exposed on at least one side of the graphene layer, forming a mask pattern from the block copolymer layer by removing one of a plurality of first region and a plurality of second regions of the block copolymer, and patterning the graphene layer in a nanoscale by using the mask pattern as an etching mask. The block copolymer layer may be formed to directly contact the graphene layer. The block copolymer layer may be formed to directly contact a region of the substrate structure that is exposed on at least one side of the graphene layer.

公开(公告)号：US20240395613A1

公开(公告)日：2024-11-28

申请号：US18794736

申请日：2024-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunwook SHIN ,  Sanghoon AHN ,  Woojin LEE ,  Kyung-Eun BYUN ,  Junghoo SHIN ,  Hyeonjin SHIN ,  Yunseong LEE

IPC: H01L21/768 ,  H01L21/285

Abstract: Provided is a method of forming an interconnect structure. The method includes preparing a substrate including a first metal layer and a first insulating layer, selectively forming a carbon layer having an sp2 bonding structure on the first metal layer, selectively forming a second insulating layer on the first insulating layer, forming a third insulating layer to cover the second insulating layer, and forming a second metal layer electrically connected to the first metal layer.

公开(公告)号：US20240266418A1

公开(公告)日：2024-08-08

申请号：US18635385

申请日：2024-04-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghyun JO ,  Jinseong HEO ,  Hyangsook LEE ,  Sangwook KIM ,  Yunseong LEE

IPC: H01L29/51 ,  H01L21/02

CPC classification number: H01L29/517 ,  H01L21/02181 ,  H01L21/02194 ,  H01L21/022 ,  H01L21/02356 ,  H01L28/40 ,  H01L29/516 ,  H01L29/513

Abstract: Disclosed herein is a thin film structure, including a first conductive layer on a dielectric layer including a plurality of layers. Each of the plurality of layers includes a dopant layer containing a dopant A and a HfO2layer to form a compound of HfxA1-xOz (0