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公开(公告)号：JPS63164742A
公开(公告)日：1988-07-08
申请号：JP31478586
申请日：1986-12-26
Applicant: TOSHIBA CORP
Inventor： OYA YASUNORI , TANAKA SHUICHI
Abstract: PURPOSE:To recover a clock stably by identifying 2-series of demodulated eye patterns by each binary identification circuit and using a signal being one series as the result of exclusive OR with the obtained output so as to obtain a recovered clock. CONSTITUTION:A reception signal is sent to phase detectors 3A, 3B via a signal distributor 2, led to identification circuits 10A, 10B via low pass filters 4A, 4B and DC amplifiers 5A, 5B and binarized. Then an EX-OR gate 11 applies exclusive OR, one series signal is formed and the result is sent from an output terminal 19 as a recovered clock. In obtaining a signal from the 2 series binary identification circuits 10A, 10B in this way, since several bits of phase difference are provided between the 2 series signals in the scrambling at the sender side and a modulator applies transmission logic operation, the signal formation of consecutive 0s or 1s is rare and the original clock signal is obtained stably by applying exclusive OR.
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公开(公告)号：JPS62266927A
公开(公告)日：1987-11-19
申请号：JP11112486
申请日：1986-05-15
Applicant: TOSHIBA CORP
Inventor： TANAKA SHUICHI
Abstract: PURPOSE:To maximize the detection/correction capability and to simplify the unit by providing a coding section, a decoding section and an address generating section so as to apply coding/decoding by a reed solomon code. CONSTITUTION:A data word constituting a code series stored in a RAM 12 is fed to a coding section 13 according to an address of an address generating section 14, and the coding section 13 generates a check word and adds it to an input data word, and the result is sent. In this case, the coding section 13 gives a coding end signal to the address generating section 14, the next address is generated and the sequential coding is applied. In case of the decoding, the word of code series stored in a RAM 22 is fed to a decoding section 23 according to an address of an address generating section 24, the decoding section 23 calculates an erasure error pattern and applies the erasure correction of the input data word and the result is sent. In this case, the decoding section 23 gives a decoding end signal to an address generating section 24, where the next address is generated. Thus, the detection/correction capability is maximized and the unit is simplified.
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公开(公告)号：JPS62154937A
公开(公告)日：1987-07-09
申请号：JP29252885
申请日：1985-12-27
Applicant: TOSHIBA CORP
Inventor： TANAKA SHUICHI
Abstract: PURPOSE:To easily adjust a carrier leak under the condition in normal operation by inputting a signal which is obtained by utilizing a clock signal during the adjustment of a DC voltage instead of a parallel data signal. CONSTITUTION:When the carrier leak is adjusted, a switching circuit 30 is switched to the side of the 2nd logic circuit 31 for adjustment and a clock after series-parallel conversion is inputted to the logic circuit 31. The fetched clock signal is frequency-divided by two through the 1st D type flip-flop 3a into two signals A and B, which are inputted to a binary-quadruplicate converter 33. Binary-quadruplicate converters 32 and 33 output quadruplicate base band signals E and F on the basis of the input binary signals A and B, and C and D as well as in normal operation.
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公开(公告)号：JPS62122334A
公开(公告)日：1987-06-03
申请号：JP11112586
申请日：1986-05-15
Applicant: TOSHIBA CORP
Inventor： TANAKA SHUICHI
Abstract: PURPOSE:To utilize at most the detection and correction capability of a reed solomon code minimized in hardware scale by using repetitively required minimum arithmetic unit by the number of times depending on the inter-code distance. CONSTITUTION:A digital data arithmetic processing unit has a coding means by a reed solomon code generating a check word by solving equation (I) and a check word pattern Pk being at least (m-1)-set of roots are obtained by equation (II). Further, a decoding means by a reed solomon code by applying erasure correction by solving equation (III) is provided to obtain an erasure pattern Yk being a root of equation by equation (IV). The detection/correction capability of the reed solomon code is enhanced at most and the titled device is simplified minimizingly. In equation (III), l=0-d-2, k=1-m, m is an erasure error number (known), Xk is the k-th error location (known), S1 is syndrome (known), Yk is the k-th erasure error pattern, and d is the minimum distance of the code, and k, l, p, j, n in equation (IV) are the same as those of equation (III).
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公开(公告)号：JPS61131602A
公开(公告)日：1986-06-19
申请号：JP25158484
申请日：1984-11-30
Applicant: Toshiba Corp
Inventor： TANAKA SHUICHI , OI TOSHIHIKO
Abstract: PURPOSE: To obtain a stable oscillating frequency with immunity to an effect of temperature change by connecting a capacitor having a sufficiently large capacitance between an inductor and a varactor diode connected directly to an ECL circuit.
CONSTITUTION: The varactor diodes D
1 , D
2 are connected in parallel with the inductor L
2 of a resonance circuit 2 in direct DC-coupling to ECL circuit 1 via the capacitors C
3 , C
4 having a sufficiently large capacitance. A bias voltage from an input terminal is fed from the inductor L
1 to the varactor diode D
1 and from the inductor L
1 to the varactor diode D
2 . Since a bias voltage of the varactor diodes D
1 , D
2 is decided by a circuit not including an element having a problem on the temperature characteristic at all, a stable oscillation output is obtained.
COPYRIGHT: (C)1986,JPO&JapioAbstract translation: 目的：通过连接电感器和直接连接到ECL电路的变容二极管之间具有足够大的电容的电容器来获得具有免受温度变化影响的稳定的振荡频率。 构成：变容二极管D1，D2与谐振电路2的电感器L2并联连接，通过具有足够大的电容的电容器C3，C4直接与ECL电路1耦合。 来自输入端子的偏置电压从电感器L1馈送到变容二极管D1，并且从电感器L1馈送到变容二极管D2。 由于变容二极管D1，D2的偏置电压由不包括具有温度特性问题的元件的电路决定，所以获得稳定的振荡输出。
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Patent Agency Ranking26.发明专利
公开(公告)号：JPH06261023A
公开(公告)日：1994-09-16
申请号：JP4656293
申请日：1993-03-08
Applicant: TOSHIBA CORP , TOSHIBA AVE KK
Inventor： TANAKA SHUICHI , FUJII YASUYUKI , UMEKI MASAHIKO
Abstract: PURPOSE:To enhance a data transmission efficiency by implementing multi-frame synchronization and interleave frame synchronization based on common synchronization information thereby reducing the number of synchronization information sets. CONSTITUTION:Frame synchronization word insertion circuits 21-I, 21-Q insert one FEC synchronization word per one FEC frame to each of I and Q series digital signals respectively and constitute one multi-frame with 5 FEC frames and multi-frame synchronization information is added to the FEC synchronization word inserted to the head FEC frame. First memories 24-I, 24-Q and 2nd memories 25-I, 25-Q are subjected to frame processing and code logic arithmetic operation circuits 23-I, 23-Q interleave each of I and Q series digital signals for each of the 5 FEC frames being one multi-frame.
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公开(公告)号：JPH0661976A
公开(公告)日：1994-03-04
申请号：JP21261092
申请日：1992-08-10
Applicant: TOSHIBA CORP , TOSHIBA AVE KK
Inventor： TANAKA SHUICHI , FUJII YASUYUKI , UMEKI MASAHIKO
Abstract: PURPOSE:To individually attain a function test, and to easily specify an abnormality generating part. CONSTITUTION:A delay circuit 26 branch-inputs data inputted to an encoding arithmetic logic circuit 24, and delays the data in a prescribed time. A selector 33 supplies encoded data error correction-encoded by the encoding arithmetic logic circuit 24 to a decoding arithmetic logic circuit 35 as necessary. A redundant bit selecting circuit 37 selects the data outputted from the delay circuit 26 in a period in which the inputted decoded data are a redundant bit part according to a switching signal from a timing generating circuit 36.
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公开(公告)号：JPH0620445A
公开(公告)日：1994-01-28
申请号：JP12393391
申请日：1991-05-28
Applicant: TOSHIBA CORP
Inventor： TANAKA SHUICHI
IPC: G11B15/02 , G11B27/02 , G11B27/024
Abstract: PURPOSE:To prevent a nonrecorded part on the side of a master from being recorded on the side of a slave by immediately stopping a dubbing operation upon completion of dubbing data recorded on the master side. CONSTITUTION:Prior to dubbing, a nonrecorded part of a tape is detected, and also its last PNO (program number) and an in-page picture number are recorded. At the time of dubbing, the last PNO and the in-page picture number are compared with a PNO and an in-page picture number, obtained by reproducing the tape at steps S1 and S2. Then, the dubbing is stopped in timing of detecting a picture ending signal of the picture data upon coincidence of the above-mentioned numbers at steps S3 and S4. Consequently, the nonrecorded part such as a waiting time, etc., of a 1st recording medium is not recorded on a 2nd recording medium, and hence inconvenience such as retrieval infeasibility, etc., caused by recording the nonrecorded part is eliminated.
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公开(公告)号：JPH04364621A
公开(公告)日：1992-12-17
申请号：JP13934991
申请日：1991-06-12
Applicant: TOSHIBA CORP
Inventor： KODAMA TOMOKO , NAKAMURA MAKOTO , TANAKA SHUICHI
Abstract: PURPOSE:To switch a line while the quality of a transmission signal is kept by starting the transmission of a standby line when the quality of the transmission signal of an active line is degraded and switching the line when synchronization is taken. CONSTITUTION:When a bit error rate reaches a prescribed rate or above, as soon as a line switching signal is sent to a line switching device 10 and a frame synchronization detector 9, the signal transmission in a standby line is started. Then the detector 9 implements frame synchronization based on a transmission signal sent through the standby line and after the frame synchronization in the standby line is confirmed, the switching device 10 is used to switch the line. Since the active line and the standby line are switched between a transmission frame and a frequency, the active and standby lines are switched without causing error correction disabling state of the signal caused when the switching is implemented in the frame of the transmission signal.
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公开(公告)号：JPH04207809A
公开(公告)日：1992-07-29
申请号：JP34035190
申请日：1990-11-30
Applicant: TOSHIBA CORP
Inventor： FUJII YASUYUKI , TANAKA SHUICHI
Abstract: PURPOSE:To shorten the integrating time and to improve the control responsiveness against the increase of the inter-code interference value by selecting the output equivalent to the prescribed number of bits of the upper or lower stage of a counter through a selector means in accordance with the inter-code interference value and using the selected output for control of the weighting value of a weighting means. CONSTITUTION:The correlation detection output o f a correlation detector 301 is applied to an up-down counter 402. Thus the counter 402 is counted up or down. Then the count output equivalent to 8 bits is selected in response to the selection signals a1, a2, a3... equivalent to the inter-code value. If the inter-code inference value is increased with occurrence of the distortion of transmission like the fading, etc., 8 bits are selected at the lower stage side of the count output. Meanwhile 8 bits are selected at the upper stage side of the count output are selected and a long integrating time is set if no fading occurs and a transmission line has a stable state.
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