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    22.
    发明专利
    未知

    公开(公告)号：FR2770930B1

    公开(公告)日：2000-03-03

    申请号：FR9714035

    申请日：1997-11-07

    Applicant: UNITED MICROELECTRONICS CORP

    Inventor： YEW TRI RUNG ,  LUR WATER ,  SUN SHIH WEI

    IPC: H01L21/02 ,  H01L21/8242 ,  H01L27/108

    Abstract: A high capacitance charge storage capacitor for a DRAM has a lower electrode in contact with one source/drain region of a transfer FET. The lower capacitor electrode includes a first layer of polysilicon deposited over part of the transfer FET and in contact with the source/drain region of the transfer FET. An oxide layer is deposited over the first polysilicon layer and then a sparse layer of hemispherical grained polysilicon is deposited on the surface of the oxide layer. The sparse layer of hemispherical grained polysilicon has grains on the order of approximately 100 nanometers across that are separated on the average by approximately 100 nanometers. The layer of oxide is etched using the sparse grains of hemispherical grained polysilicon as a mask, with the etch process stopping on the surface of the first layer of polysilicon. A second layer of polysilicon is deposited over the remaining grains of hemispherical grained polysilicon and over the column-shaped portions of the oxide layer left by the etching stop. A capacitor dielectric is formed over the second layer of polysilicon and then an upper capacitor electrode is provided.

    High density dynamic random access memory formation
    26.
    发明专利
    High density dynamic random access memory formation 未知

    公开(公告)号：FR2763174A1

    公开(公告)日：1998-11-13

    申请号：FR9705665

    申请日：1997-05-07

    Applicant: UNITED MICROELECTRONICS CORP

    Inventor： SUN SHIH WEI ,  YEW TRI RUNG

    IPC: H01L21/3205 ,  H01L21/306 ,  H01L21/336 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/78

    Abstract: Formation of a dynamic random access memory (DRAM) comprises (i) providing an insulating layer over an active region of a substrate (50), (ii) forming transfer transistors on the active region, the first transistor including a gate electrode over the insulating layer and first and second source/drain regions (82, 84) formed in the substrate, the second transistor including a second gate electrode over the insulating layer and the second and third source/drain regions, the transistors sharing the second source/drain region, (ii) forming an etch stop layer (90) over the first and second gate electrodes and over the first, second and third source/drain regions, (iii) forming a dielectric layer (96) over the etch stop layer, (iv) etching through the dielectric layer above the second source/drain region, stopping the etching process on the etch stop layer, performing a further etching process to etch through the etch stop layer and then forming a bit line contact (112) to the second source/drain region, and (v) etching through the dielectric layer above the third source/drain region, stopping the etching process on the etch stop layer, performing a further etching process to etch through the etch stop layer and then forming a charge storage capacitor having an electrode (98) electrically connected to the third source/drain region and comprising a layer of hemispherical grained polysilicon.

    29.
    发明专利
    未知

    公开(公告)号：FR2774809B1

    公开(公告)日：2002-07-12

    申请号：FR9812017

    申请日：1998-09-25

    Applicant: UNITED MICROELECTRONICS CORP

    Inventor： YEW TRI RUNG ,  LUR WATER ,  SUN SHIH WEI ,  HUANG YIMIN

    IPC: H01L21/28 ,  H01L21/336 ,  H01L21/768 ,  H01L23/522 ,  H01L29/78 ,  H01L23/528

    Abstract: A method for forming a barrier layer comprising the steps of first providing a semiconductor substrate that has a conductive layer already formed thereon. Then, a dielectric layer such as an organic low-k dielectric layer is deposited over the conductive layer and the semiconductor substrate. Next, an opening in formed in the dielectric layer exposing the conductive layer. Thereafter, a first barrier layer is deposited into the opening and the surrounding area. The first barrier layer can be a silicon-contained layer or a doped silicon (doped-Si) layer formed by a plasma-enhanced chemical vapor deposition (PECVD) method, a low-pressure chemical vapor deposition (LPCVD) method, an electron beam evaporation method or a sputtering method. Finally, a second barrier layer is formed over the first barrier layer. The second barrier layer can be a titanium/titanium nitride (Ti/TiN) layer, a tungsten nitride (WN) layer, a tantalum (Ta) layer or a tantalum nitride (TaN) layer.

    30.
    发明专利
    未知

    公开(公告)号：FR2765397B1

    公开(公告)日：2001-06-08

    申请号：FR9800712

    申请日：1998-01-23

    Applicant: UNITED MICROELECTRONICS CORP

    Inventor： YEW TRI RUNG ,  LUR WATER ,  SUN SHIH WEI

    IPC: H01L27/108 ,  H01L21/02 ,  H01L21/8242

    Abstract: A method of fabricating a DRAM device to reduce the stress and enhance the adhesion between the top electrode and the interlevel dielectric layer, includes forming a titanium layer between the top electrode and the interlevel dielectric layer. A titanium oxide layer and a titanium silicide are formed between the titanium layer and the interlevel dielectric layer in post thermal procedures, which enhances the adhesion and avoids cracks and leakage current between the top electrode and the interlevel dielectric layer.

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