公开(公告)号：US20230078993A1

公开(公告)日：2023-03-16

申请号：US17989710

申请日：2022-11-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Hsin Hsu ,  Huan-Chi Ma ,  Chien-Wen Yu ,  Shih-Min Chou ,  Nien-Ting Ho ,  Ti-Bin Chen

IPC: H01L29/49 ,  H01L29/423 ,  H01L29/40 ,  H01L29/66

Abstract: A semiconductor device includes a substrate and a gate structure. The gate structure is disposed on the substrate, and the gate structure includes a titanium nitride barrier layer a titanium aluminide layer, and a middle layer. The titanium aluminide layer is disposed on the titanium nitride barrier layer, and the middle layer is disposed between the titanium aluminide layer and the titanium nitride barrier layer. The middle layer is directly connected with the titanium aluminide layer and the titanium nitride barrier layer, and the middle layer includes titanium and nitrogen. A concentration of nitrogen in the middle layer is gradually decreased in a vertical direction towards an interface between the middle layer and the titanium aluminide layer.

公开(公告)号：US11271078B2

公开(公告)日：2022-03-08

申请号：US16836953

申请日：2020-04-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shi-You Liu ,  Tsai-Yu Wen ,  Ching-I Li ,  Ya-Yin Hsiao ,  Chih-Chiang Wu ,  Yu-Chun Liu ,  Ti-Bin Chen ,  Shao-Ping Chen ,  Huan-Chi Ma ,  Chien-Wen Yu

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L21/324 ,  H01L21/265 ,  H01L21/8234

Abstract: A p-type field effect transistor (pFET) includes a gate structure on a substrate, a channel region in the substrate directly under the gate structure, and a source/drain region adjacent to two sides of the gate structure. Preferably, the channel region includes a top portion and a bottom portion, in which a concentration of germanium in the bottom portion is lower than a concentration of germanium in the top portion and a depth of the top portion is equal to a depth of the bottom portion.

公开(公告)号：US20210257471A1

公开(公告)日：2021-08-19

申请号：US17246726

申请日：2021-05-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Fan Li ,  Kuo-Chin Hung ,  Wen-Yi Teng ,  Ti-Bin Chen

IPC: H01L29/417 ,  H01L29/49 ,  H01L29/423 ,  H01L21/311 ,  H01L29/66 ,  H01L29/161 ,  H01L29/78

Abstract: A first gate and a second gate are formed on a substrate with a gap between the first and second gates. The first gate has a first sidewall. The second gate has a second sidewall directly facing the first sidewall. A first sidewall spacer is disposed on the first sidewall. A second sidewall spacer is disposed on the second sidewall. A contact etch stop layer is deposited on the first and second gates and on the first and second sidewall spacers. The contact etch stop layer is subjected to a tilt-angle plasma etching process to trim a corner portion of the contact etch stop layer. An inter-layer dielectric layer is then deposited on the contact etch stop layer and into the gap.

公开(公告)号：US20200321442A1

公开(公告)日：2020-10-08

申请号：US16907287

申请日：2020-06-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Fan Li ,  Wen-Yen Huang ,  Shih-Min Chou ,  Zhen Wu ,  Nien-Ting Ho ,  Chih-Chiang Wu ,  Ti-Bin Chen

IPC: H01L29/49 ,  H01L29/40 ,  H01L27/092

Abstract: A semiconductor device includes a substrate having a first region and a second region and a gate structure on the first region and the second region of the substrate. The gate structure includes a first bottom barrier metal (BBM) layer on the first region and the second region, a first work function metal (WFM) layer on the first region; and a diffusion barrier layer on a top surface and a sidewall of the first WFM layer on the first region and the first BBM layer on the second region. Preferably, a thickness of the first BBM layer on the second region is less than a thickness of the first BBM layer on the first region.

公开(公告)号：US20200006517A1

公开(公告)日：2020-01-02

申请号：US16053665

申请日：2018-08-02

Applicant: United Microelectronics Corp.

Inventor： Yi-Fan Li ,  Po-Ching Su ,  Cheng-Chia Liu ,  Yen-Tsai Yi ,  Wei-Chuan Tsai ,  Chih-Chiang Wu ,  Ti-Bin Chen ,  Ching-Chu Tseng

IPC: H01L29/66 ,  H01L29/78 ,  H01L23/31

Abstract: A structure of semiconductor device includes a gate structure, disposed on a substrate. A spacer is disposed on a sidewall of the gate structure, wherein the spacer is an l-like structure. A first doped region is disposed in the substrate at two sides of the gate structure. A second doped region is disposed in the substrate at the two sides of the gate structure, overlapping the first doped region. A silicide layer is disposed on the substrate within the second doped region, separating from the spacer by a distance. A dielectric layer covers over the second doped region and the gate structure with the spacer.

公开(公告)号：US20190198628A1

公开(公告)日：2019-06-27

申请号：US15853867

申请日：2017-12-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Fan Li ,  Kuo-Chin Hung ,  Wen-Yi Teng ,  Ti-Bin Chen

IPC: H01L29/417 ,  H01L29/49 ,  H01L29/423 ,  H01L29/161 ,  H01L29/78 ,  H01L29/66 ,  H01L21/311

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes first and second metal gates on a substrate with a gap therebetween. The first metal gate has a first sidewall, and the second metal gate has a second sidewall directly facing the first sidewall. A contact etch stop layer (CESL) is disposed within the gap and extends along the first and second sidewalls. The CESL has a first top portion adjacent to a top surface of the first metal gate and a second top portion adjacent to a top surface of the second metal gate. The first top portion and the second top portion have a trapezoid cross-sectional profile. A first sidewall spacer is disposed on the first sidewall and between the CESL and the first metal gate. A second sidewall spacer is disposed on the second sidewall and between the CESL and the second metal gate.

公开(公告)号：US08692334B2

公开(公告)日：2014-04-08

申请号：US13949230

申请日：2013-07-24

Applicant: United Microelectronics Corp.

Inventor： Chun-Mao Chiou ,  Ti-Bin Chen ,  Tsung-Min Kuo ,  Shyan-Liang Chou ,  Yao-Chang Wang ,  Chi-Sheng Tseng ,  Jie-Ning Yang ,  Po-Jui Liao

IPC: H01L21/70

CPC classification number: H01L27/0629

Abstract: A method of manufacturing a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, a transistor is positioned in the transistor region and a resistor is positioned in the resistor region; forming a dielectric layer exposing tops of the transistor and the resistor on the substrate; performing a first etching process to remove portions of the resistor to form two first trenches respectively at two opposite ends of the resistor; forming a patterned protecting layer in the resistor region; performing a second etching process to remove a dummy gate of the transistor to form a second trench in the transistor region; and forming a metal layer filling the first trenches and the second trench.

Abstract translation: 一种制造与具有金属栅极的晶体管集成的电阻器的方法包括提供具有晶体管区域和限定在其上的电阻器区域的衬底，晶体管位于晶体管区域中，并且电阻器位于电阻器区域中; 形成暴露所述晶体管顶部和所述基板上的所述电阻器的电介质层; 执行第一蚀刻工艺以去除电阻器的部分以分别在电阻器的两个相对端处形成两个第一沟槽; 在所述电阻器区域中形成图案化保护层; 执行第二蚀刻工艺以去除晶体管的伪栅极以在晶体管区域中形成第二沟槽; 以及形成填充所述第一沟槽和所述第二沟槽的金属层。

公开(公告)号：US20250159964A1

公开(公告)日：2025-05-15

申请号：US19021275

申请日：2025-01-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Fan Li ,  Wen-Yen Huang ,  Shih-Min Chou ,  Zhen Wu ,  Nien-Ting Ho ,  Chih-Chiang Wu ,  Ti-Bin Chen

IPC: H10D64/66 ,  H10D64/01 ,  H10D84/85

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a first region and a second region, forming a first bottom barrier metal (BBM) layer on the first region and the second region, forming a first work function metal (WFM) layer on the first BBM layer on the first region and the second region, and then forming a diffusion barrier layer on the first WFM layer.

公开(公告)号：US12237394B2

公开(公告)日：2025-02-25

申请号：US18226262

申请日：2023-07-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Fan Li ,  Wen-Yen Huang ,  Shih-Min Chou ,  Zhen Wu ,  Nien-Ting Ho ,  Chih-Chiang Wu ,  Ti-Bin Chen

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/40

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a first region and a second region, forming a first bottom barrier metal (BBM) layer on the first region and the second region, forming a first work function metal (WFM) layer on the first BBM layer on the first region and the second region, and then forming a diffusion barrier layer on the first WFM layer.

公开(公告)号：US20240332087A1

公开(公告)日：2024-10-03

申请号：US18739286

申请日：2024-06-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Fan Li ,  Po-Ching Su ,  Yu-Fu Wang ,  Min-Hua Tsai ,  Ti-Bin Chen ,  Chih-Chiang Wu ,  Tzu-Chin Wu

IPC: H01L21/8234 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L21/823437 ,  H01L21/823462 ,  H01L21/823481 ,  H01L29/4232 ,  H01L29/78

Abstract: A method for fabricating a semiconductor device includes the steps of forming a metal gate on a substrate, a spacer around the metal gate, and a first interlayer dielectric (ILD) layer around the spacer, performing a plasma treatment process to transform the spacer into a first bottom portion and a first top portion, performing a cleaning process to remove the first top portion, and forming a second ILD layer on the metal gate and the first ILD layer.