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    Resistor integrated with transistor having metal gate
    1.
    发明授权
    Resistor integrated with transistor having metal gate 有权
    与具有金属栅极的晶体管集成的电阻器

    公开(公告)号：US08692334B2

    公开(公告)日：2014-04-08

    申请号：US13949230

    申请日：2013-07-24

    Applicant: United Microelectronics Corp.

    Inventor： Chun-Mao Chiou ,  Ti-Bin Chen ,  Tsung-Min Kuo ,  Shyan-Liang Chou ,  Yao-Chang Wang ,  Chi-Sheng Tseng ,  Jie-Ning Yang ,  Po-Jui Liao

    IPC: H01L21/70

    CPC classification number: H01L27/0629

    Abstract: A method of manufacturing a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, a transistor is positioned in the transistor region and a resistor is positioned in the resistor region; forming a dielectric layer exposing tops of the transistor and the resistor on the substrate; performing a first etching process to remove portions of the resistor to form two first trenches respectively at two opposite ends of the resistor; forming a patterned protecting layer in the resistor region; performing a second etching process to remove a dummy gate of the transistor to form a second trench in the transistor region; and forming a metal layer filling the first trenches and the second trench.

    Abstract translation: 一种制造与具有金属栅极的晶体管集成的电阻器的方法包括提供具有晶体管区域和限定在其上的电阻器区域的衬底，晶体管位于晶体管区域中，并且电阻器位于电阻器区域中; 形成暴露所述晶体管顶部和所述基板上的所述电阻器的电介质层; 执行第一蚀刻工艺以去除电阻器的部分以分别在电阻器的两个相对端处形成两个第一沟槽; 在所述电阻器区域中形成图案化保护层; 执行第二蚀刻工艺以去除晶体管的伪栅极以在晶体管区域中形成第二沟槽; 以及形成填充所述第一沟槽和所述第二沟槽的金属层。

    RESISTOR INTEGRATED WITH TRANSISTOR HAVING METAL GATE
    4.
    发明申请
    RESISTOR INTEGRATED WITH TRANSISTOR HAVING METAL GATE 有权
    电容器与带有金属栅的晶体管集成

    公开(公告)号：US20130307084A1

    公开(公告)日：2013-11-21

    申请号：US13949230

    申请日：2013-07-24

    Applicant: United Microelectronics Corp.

    Inventor： Chun-Mao Chiou ,  Ti-Bin Chen ,  Tsung-Min Kuo ,  Shyan-Liang Chou ,  Yao-Chang Wang ,  Chi-Sheng Tseng ,  Jie-Ning Yang ,  Po-Jui Liao

    IPC: H01L27/06

    CPC classification number: H01L27/0629

    Abstract: A method of manufacturing a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, a transistor is positioned in the transistor region and a resistor is positioned in the resistor region; forming a dielectric layer exposing tops of the transistor and the resistor on the substrate; performing a first etching process to remove portions of the resistor to form two first trenches respectively at two opposite ends of the resistor; forming a patterned protecting layer in the resistor region; performing a second etching process to remove a dummy gate of the transistor to form a second trench in the transistor region; and forming a metal layer filling the first trenches and the second trench.

    Abstract translation: 一种制造与具有金属栅极的晶体管集成的电阻器的方法包括提供具有晶体管区域和限定在其上的电阻器区域的衬底，晶体管位于晶体管区域中，并且电阻器位于电阻器区域中; 形成暴露所述晶体管顶部和所述基板上的所述电阻器的电介质层; 执行第一蚀刻工艺以去除电阻器的部分以分别在电阻器的两个相对端处形成两个第一沟槽; 在所述电阻器区域中形成图案化保护层; 执行第二蚀刻工艺以去除晶体管的伪栅极以在晶体管区域中形成第二沟槽; 以及形成填充所述第一沟槽和所述第二沟槽的金属层。

    SEMICONDUCTOR STRUCTURE HAVING TRIMMING SPACERS
    6.
    发明申请
    SEMICONDUCTOR STRUCTURE HAVING TRIMMING SPACERS 有权
    具有切割间隔的半导体结构

    公开(公告)号：US20150137197A1

    公开(公告)日：2015-05-21

    申请号：US14608165

    申请日：2015-01-28

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Shyan-Liang Chou ,  Tsung-Min Kuo ,  Po-Wen Su ,  Chun-Mao Chiou ,  Feng-Mou Chen

    IPC: H01L29/78 ,  H01L29/49

    CPC classification number: H01L29/4983 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7843

    Abstract: A semiconductor structure includes a substrate, a gate electrode disposed on the substrate, wherein the gate electrode has a first top surface. Agate dielectric layer is disposed between the substrate and the gate electrode. A silicon carbon nitride spacer surrounds the gate electrode, wherein the silicon carbon nitride spacer has a second top surface not higher than the first top surface. A silicon oxide spacer surrounds the silicon carbon nitride spacer.

    Abstract translation: 半导体结构包括衬底，设置在衬底上的栅电极，其中栅电极具有第一顶表面。 玛瑙电介质层设置在基板和栅电极之间。 硅碳氮化物间隔物环绕栅电极，其中硅氮化物间隔物具有不高于第一顶表面的第二顶表面。 硅氧化物间隔物包围硅氮化硅间隔物。

    Semiconductor structure having trimming spacers
    8.
    发明授权
    Semiconductor structure having trimming spacers 有权
    具有修整间隔物的半导体结构

    公开(公告)号：US09117904B2

    公开(公告)日：2015-08-25

    申请号：US14608165

    申请日：2015-01-28

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Shyan-Liang Chou ,  Tsung-Min Kuo ,  Po-Wen Su ,  Chun-Mao Chiou ,  Feng-Mou Chen

    IPC: H01L29/76 ,  H01L29/78 ,  H01L29/49

    CPC classification number: H01L29/4983 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7843

    Abstract: A semiconductor structure includes a substrate, a gate electrode disposed on the substrate, wherein the gate electrode has a first top surface. Agate dielectric layer is disposed between the substrate and the gate electrode. A silicon carbon nitride spacer surrounds the gate electrode, wherein the silicon carbon nitride spacer has a second top surface not higher than the first top surface. A silicon oxide spacer surrounds the silicon carbon nitride spacer.

    Abstract translation: 半导体结构包括衬底，设置在衬底上的栅电极，其中栅电极具有第一顶表面。 玛瑙电介质层设置在基板和栅电极之间。 硅碳氮化物间隔物环绕栅电极，其中硅氮化物间隔物具有不高于第一顶表面的第二顶表面。 硅氧化物间隔物包围硅氮化硅间隔物。

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