公开(公告)号：US20140127892A1

公开(公告)日：2014-05-08

申请号：US14135520

申请日：2013-12-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Jui Liao ,  Tsung-Lung Tsai ,  Chien-Ting Lin ,  Shao-Hua Hsu ,  Yeng-Peng Wang ,  Chun-Hsien Lin ,  Chan-Lon Yang ,  Guang-Yaw Hwang ,  Shin-Chi Chen ,  Hung-Ling Shih ,  Jiunn-Hsiung Liao ,  Chia-Wen Liang

IPC: H01L21/8238

CPC classification number: H01L29/78 ,  H01L21/823842 ,  H01L21/82385 ,  H01L29/66545

Abstract: A method of manufacturing a semiconductor device having metal gate includes providing a substrate having a first transistor and a second transistor formed thereon, the first transistor having a first gate trench formed therein, forming a first work function metal layer in the first gate trench, forming a sacrificial masking layer in the first gate trench, removing a portion of the sacrificial masking layer to expose a portion of the first work function metal layer, removing the exposed first function metal layer to form a U-shaped work function metal layer in the first gate trench, and removing the sacrificial masking layer. The first transistor includes a first conductivity type and the second transistor includes a second conductivity type. The first conductivity type and the second conductivity type are complementary.

Abstract translation: 一种制造具有金属栅极的半导体器件的方法包括：提供具有形成在其上的第一晶体管和第二晶体管的衬底，所述第一晶体管具有形成在其中的第一栅极沟槽，在所述第一栅极沟槽中形成第一功函数金属层， 在第一栅极沟槽中的牺牲掩模层，去除牺牲掩模层的一部分以暴露第一功函数金属层的一部分，去除暴露的第一功能金属层，以在第一栅极沟槽中的第一栅极沟槽中形成U形功函数金属层 栅极沟槽，以及去除牺牲掩模层。 第一晶体管包括第一导电类型，第二晶体管包括第二导电类型。 第一导电类型和第二导电类型是互补的。

公开(公告)号：US08692334B2

公开(公告)日：2014-04-08

申请号：US13949230

申请日：2013-07-24

Applicant: United Microelectronics Corp.

Inventor： Chun-Mao Chiou ,  Ti-Bin Chen ,  Tsung-Min Kuo ,  Shyan-Liang Chou ,  Yao-Chang Wang ,  Chi-Sheng Tseng ,  Jie-Ning Yang ,  Po-Jui Liao

IPC: H01L21/70

CPC classification number: H01L27/0629

Abstract: A method of manufacturing a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, a transistor is positioned in the transistor region and a resistor is positioned in the resistor region; forming a dielectric layer exposing tops of the transistor and the resistor on the substrate; performing a first etching process to remove portions of the resistor to form two first trenches respectively at two opposite ends of the resistor; forming a patterned protecting layer in the resistor region; performing a second etching process to remove a dummy gate of the transistor to form a second trench in the transistor region; and forming a metal layer filling the first trenches and the second trench.

Abstract translation: 一种制造与具有金属栅极的晶体管集成的电阻器的方法包括提供具有晶体管区域和限定在其上的电阻器区域的衬底，晶体管位于晶体管区域中，并且电阻器位于电阻器区域中; 形成暴露所述晶体管顶部和所述基板上的所述电阻器的电介质层; 执行第一蚀刻工艺以去除电阻器的部分以分别在电阻器的两个相对端处形成两个第一沟槽; 在所述电阻器区域中形成图案化保护层; 执行第二蚀刻工艺以去除晶体管的伪栅极以在晶体管区域中形成第二沟槽; 以及形成填充所述第一沟槽和所述第二沟槽的金属层。

公开(公告)号：US09240459B2

公开(公告)日：2016-01-19

申请号：US13773635

申请日：2013-02-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuang-Hung Huang ,  Jie-Ning Yang ,  Yao-Chang Wang ,  Chi-Sheng Tseng ,  Po-Jui Liao ,  Shih-Chang Chang

IPC: H01L29/66 ,  H01L21/768 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/66545 ,  H01L21/76801 ,  H01L21/76834 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6653

Abstract: A semiconductor process includes the following step. A stacked structure is formed on a substrate. A contact etch stop layer is formed to cover the stacked structure and the substrate. A material layer is formed on the substrate and exposes a top part of the contact etch stop layer covering the stacked structure. The top part is redressed.

Abstract translation: 半导体工艺包括以下步骤。 在基板上形成层叠结构。 形成接触蚀刻停止层以覆盖层叠结构和基板。 在衬底上形成材料层并暴露覆盖层叠结构的接触蚀刻停止层的顶部。 顶部被纠正。

公开(公告)号：US08999830B2

公开(公告)日：2015-04-07

申请号：US14135520

申请日：2013-12-19

Applicant: United Microelectronics Corp.

Inventor： Po-Jui Liao ,  Tsung-Lung Tsai ,  Chien-Ting Lin ,  Shao-Hua Hsu ,  Yeng-Peng Wang ,  Chun-Hsien Lin ,  Chan-Lon Yang ,  Guang-Yaw Hwang ,  Shin-Chi Chen ,  Hung-Ling Shih ,  Jiunn-Hsiung Liao ,  Chia-Wen Liang

IPC: H01L21/3205 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L29/78 ,  H01L21/823842 ,  H01L21/82385 ,  H01L29/66545

Abstract: A method of manufacturing a semiconductor device having metal gate includes providing a substrate having a first transistor and a second transistor formed thereon, the first transistor having a first gate trench formed therein, forming a first work function metal layer in the first gate trench, forming a sacrificial masking layer in the first gate trench, removing a portion of the sacrificial masking layer to expose a portion of the first work function metal layer, removing the exposed first function metal layer to form a U-shaped work function metal layer in the first gate trench, and removing the sacrificial masking layer. The first transistor includes a first conductivity type and the second transistor includes a second conductivity type. The first conductivity type and the second conductivity type are complementary.

Abstract translation: 一种制造具有金属栅极的半导体器件的方法包括：提供具有形成在其上的第一晶体管和第二晶体管的衬底，所述第一晶体管具有形成在其中的第一栅极沟槽，在所述第一栅极沟槽中形成第一功函数金属层， 在第一栅极沟槽中的牺牲掩模层，去除牺牲掩模层的一部分以暴露第一功函数金属层的一部分，去除暴露的第一功能金属层，以在第一栅极沟槽中的第一栅极沟槽中形成U形功函数金属层 栅极沟槽，以及去除牺牲掩模层。 第一晶体管包括第一导电类型，第二晶体管包括第二导电类型。 第一导电类型和第二导电类型是互补的。

公开(公告)号：US20140339652A1

公开(公告)日：2014-11-20

申请号：US14449157

申请日：2014-08-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Guang-Yaw Hwang ,  Chun-Hsien Lin ,  Hung-Ling Shih ,  Jiunn-Hsiung Liao ,  Zhi-Cheng Lee ,  Shao-Hua Hsu ,  Yi-Wen Chen ,  Cheng-Guo Chen ,  Jung-Tsung Tseng ,  Chien-Ting Lin ,  Tong-Jyun Huang ,  Jie-Ning Yang ,  Tsung-Lung Tsai ,  Po-Jui Liao ,  Chien-Ming Lai ,  Ying-Tsung Chen ,  Cheng-Yu Ma ,  Wen-Han Hung ,  Che-Hua Hsu

IPC: H01L29/51 ,  H01L29/49

CPC classification number: H01L29/517 ,  H01L21/28088 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7846

Abstract: A semiconductor device with oxygen-containing metal gates includes a substrate, a gate dielectric layer and a multi-layered stack structure. The multi-layered stack structure is disposed on the substrate. At least one layer of the multi-layered stack structure includes a work function metal layer. The concentration of oxygen in the side of one layer of the multi-layered stack structure closer to the gate dielectric layer is less than that in the side of one layer of the multi-layered stack structure opposite to the gate dielectric layer.

Abstract translation: 具有含氧金属栅极的半导体器件包括衬底，栅介质层和多层堆叠结构。 多层堆叠结构设置在基板上。 多层堆叠结构的至少一层包括功函数金属层。 更靠近栅介质层的多层堆叠结构的一层侧的氧的浓度小于与栅介质层相反的多层堆叠结构的一层的一侧的浓度。

公开(公告)号：US20130307084A1

公开(公告)日：2013-11-21

申请号：US13949230

申请日：2013-07-24

Applicant: United Microelectronics Corp.

Inventor： Chun-Mao Chiou ,  Ti-Bin Chen ,  Tsung-Min Kuo ,  Shyan-Liang Chou ,  Yao-Chang Wang ,  Chi-Sheng Tseng ,  Jie-Ning Yang ,  Po-Jui Liao

IPC: H01L27/06

CPC classification number: H01L27/0629

Abstract: A method of manufacturing a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, a transistor is positioned in the transistor region and a resistor is positioned in the resistor region; forming a dielectric layer exposing tops of the transistor and the resistor on the substrate; performing a first etching process to remove portions of the resistor to form two first trenches respectively at two opposite ends of the resistor; forming a patterned protecting layer in the resistor region; performing a second etching process to remove a dummy gate of the transistor to form a second trench in the transistor region; and forming a metal layer filling the first trenches and the second trench.

Abstract translation: 一种制造与具有金属栅极的晶体管集成的电阻器的方法包括提供具有晶体管区域和限定在其上的电阻器区域的衬底，晶体管位于晶体管区域中，并且电阻器位于电阻器区域中; 形成暴露所述晶体管顶部和所述基板上的所述电阻器的电介质层; 执行第一蚀刻工艺以去除电阻器的部分以分别在电阻器的两个相对端处形成两个第一沟槽; 在所述电阻器区域中形成图案化保护层; 执行第二蚀刻工艺以去除晶体管的伪栅极以在晶体管区域中形成第二沟槽; 以及形成填充所述第一沟槽和所述第二沟槽的金属层。

公开(公告)号：US20140242770A1

公开(公告)日：2014-08-28

申请号：US13773635

申请日：2013-02-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuang-Hung Huang ,  Jie-Ning Yang ,  Yao-Chang Wang ,  Chi-Sheng Tseng ,  Po-Jui Liao ,  Shih-Chang Chang

IPC: H01L29/66

CPC classification number: H01L29/66545 ,  H01L21/76801 ,  H01L21/76834 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6653

Abstract: A semiconductor process includes the following step. A stacked structure is formed on a substrate. A contact etch stop layer is formed to cover the stacked structure and the substrate. A material layer is formed on the substrate and exposes a top part of the contact etch stop layer covering the stacked structure. The top part is redressed.

Abstract translation: 半导体工艺包括以下步骤。 在基板上形成层叠结构。 形成接触蚀刻停止层以覆盖层叠结构和基板。 在衬底上形成材料层并暴露覆盖层叠结构的接触蚀刻停止层的顶部。 顶部被纠正。

公开(公告)号：US20140103443A1

公开(公告)日：2014-04-17

申请号：US14135588

申请日：2013-12-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Jui Liao ,  Tsung-Lung Tsai ,  Chien-Ting Lin ,  Shao-Hua Hsu ,  Yeng-Peng Wang ,  Chun-Hsien Lin ,  Chan-Lon Yang ,  Guang-Yaw Hwang ,  Shin-Chi Chen ,  Hung-Ling Shih ,  Jiunn-Hsiung Liao ,  Chia-Wen Liang

IPC: H01L29/78

CPC classification number: H01L29/78 ,  H01L21/823842 ,  H01L21/82385 ,  H01L29/66545

Abstract: A semiconductor device having a metal gate includes a substrate having a first gate trench and a second gate trench formed thereon, a gate dielectric layer respectively formed in the first gate trench and the second gate trench, a first work function metal layer formed on the gate dielectric layer in the first gate trench and the second gate trench, a second work function metal layer respectively formed in the first gate trench and the second gate trench, and a filling metal layer formed on the second work function metal layer. An opening width of the second gate trench is larger than an opening width of the first gate trench. An upper area of the second work function metal layer in the first gate trench is wider than a lower area of the second work function metal layer in the first gate trench.

Abstract translation: 具有金属栅极的半导体器件包括具有形成在其上的第一栅极沟槽和第二栅极沟槽的衬底，分别形成在第一栅极沟槽和第二栅极沟槽中的栅极电介质层，形成在栅极上的第一功函数金属层 第一栅极沟槽和第二栅极沟槽中的介电层，分别形成在第一栅极沟槽和第二栅极沟槽中的第二功函数金属层和形成在第二功函数金属层上的填充金属层。 第二栅极沟槽的开口宽度大于第一栅极沟槽的开口宽度。 第一栅极沟槽中的第二功函数金属层的上部区域比第一栅极沟槽中的第二功函数金属层的下部区域宽。

公开(公告)号：US08952451B2

公开(公告)日：2015-02-10

申请号：US14135588

申请日：2013-12-20

Applicant: United Microelectronics Corp.

Inventor： Po-Jui Liao ,  Tsung-Lung Tsai ,  Chien-Ting Lin ,  Shao-Hua Hsu ,  Yeng-Peng Wang ,  Chun-Hsien Lin ,  Chan-Lon Yang ,  Guang-Yaw Hwang ,  Shin-Chi Chen ,  Hung-Ling Shih ,  Jiunn-Hsiung Liao ,  Chia-Wen Liang

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8238

CPC classification number: H01L29/78 ,  H01L21/823842 ,  H01L21/82385 ,  H01L29/66545

Abstract: A semiconductor device having a metal gate includes a substrate having a first gate trench and a second gate trench formed thereon, a gate dielectric layer respectively formed in the first gate trench and the second gate trench, a first work function metal layer formed on the gate dielectric layer in the first gate trench and the second gate trench, a second work function metal layer respectively formed in the first gate trench and the second gate trench, and a filling metal layer formed on the second work function metal layer. An opening width of the second gate trench is larger than an opening width of the first gate trench. An upper area of the second work function metal layer in the first gate trench is wider than a lower area of the second work function metal layer in the first gate trench.

Abstract translation: 具有金属栅极的半导体器件包括具有形成在其上的第一栅极沟槽和第二栅极沟槽的衬底，分别形成在第一栅极沟槽和第二栅极沟槽中的栅极电介质层，形成在栅极上的第一功函数金属层 第一栅极沟槽和第二栅极沟槽中的介电层，分别形成在第一栅极沟槽和第二栅极沟槽中的第二功函数金属层和形成在第二功函数金属层上的填充金属层。 第二栅极沟槽的开口宽度大于第一栅极沟槽的开口宽度。 第一栅极沟槽中的第二功函数金属层的上部区域比第一栅极沟槽中的第二功函数金属层的下部区域宽。