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公开(公告)号：CN106395737A
公开(公告)日：2017-02-15
申请号：CN201610843146.1
申请日：2016-09-23
Applicant: 吉林大学
CPC classification number: B81C1/00349 , B81C2201/0174 , B82B3/0009 , B82Y40/00
Abstract: 一种利用等离子刻蚀机的垂直电场分布制备材料表面形态呈梯度变化的微纳米级结构阵列功能材料的方法，属于材料科学技术领域。本发明结合倾斜放置的样品和等离子刻蚀机的垂直电场在多种材料中引入梯度结构阵列，整个过程操作简便，通过调控刻蚀条件和基底材料的种类可以在多种材料(聚合物、氧化物、金属等)中引入形态可控的梯度结构。本发明步骤简单，根据具体使用材料更换相应的刻蚀气体即可完成制备目的结构样品，实例中所制备的梯度微纳米级结构是二维尺度上的，其在微纳米级形态结构上是呈梯度变化的，通过在材料表面的后处理，可以更加灵活的应用。
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公开(公告)号：CN105633062A
公开(公告)日：2016-06-01
申请号：CN201510591151.3
申请日：2015-09-16
Applicant: 意法半导体(格勒诺布尔2)公司
IPC: H01L25/00 , H01L25/065 , H01L23/31 , H01L23/52
CPC classification number: H01L23/562 , B81B2207/098 , B81C3/001 , B81C2201/0174 , B81C2203/0771 , H01L21/4853 , H01L21/561 , H01L21/563 , H01L23/14 , H01L23/3114 , H01L23/315 , H01L23/3157 , H01L23/49811 , H01L23/49838 , H01L23/564 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2224/16225 , H01L2225/06513 , H01L2225/06555 , H01L2924/15311 , H01L2924/18161
Abstract: 本公开的实施方式涉及一种用于制造电子器件的方法以及电子器件，其中第一和第二集成电路芯片(2，5)被面对地并且彼此相距一定距离堆叠，多个电连接柱(11)和至少一个保护性阻挡件(7，28，29，35)介于所述芯片之间，从而在所述芯片的相互相对的局部区域(9，10)之间界定自由空间(8)，并且包封块(12)在具有较小的安装面的芯片(2)周围以及在另一芯片(5)的安装面的外围之上延伸；并且其中所述电连接柱以及所述保护性阻挡件出于同步制造的目的而由至少一种相同的金属材料制成。
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公开(公告)号：US11932533B2
公开(公告)日：2024-03-19
申请号：US17128638
申请日：2020-12-21
Applicant: Infineon Technologies AG
Inventor： Marc Fueldner , Andreas Wiesbauer , Athanasios Kollias
CPC classification number: B81C1/0023 , B81B7/02 , B81C1/00158 , B81C1/00182 , B81C1/00293 , B81B2201/0257 , B81B2203/0127 , B81B2207/012 , B81B2207/03 , B81C2201/0174 , B81C2203/0792
Abstract: A triple-membrane MEMS device includes a first membrane, a second membrane and a third membrane spaced apart from one another, wherein the second membrane is between the first membrane and the third membrane, a sealed low pressure chamber between the first membrane and the third membrane, a first stator and a second stator in the sealed low pressure chamber, and a signal processing circuit configured to read-out output signals of the triple-membrane MEMS device.
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公开(公告)号：US20160148880A1
公开(公告)日：2016-05-26
申请号：US14852711
申请日：2015-09-14
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： Romain Coffy , Julien Pruvost
IPC: H01L23/00 , H01L25/00 , H01L23/498 , H01L21/56 , H01L23/31 , H01L23/14 , H01L25/065 , H01L21/48
CPC classification number: H01L23/562 , B81B2207/098 , B81C3/001 , B81C2201/0174 , B81C2203/0771 , H01L21/4853 , H01L21/561 , H01L21/563 , H01L23/14 , H01L23/3114 , H01L23/315 , H01L23/3157 , H01L23/49811 , H01L23/49838 , H01L23/564 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2224/16225 , H01L2225/06513 , H01L2225/06555 , H01L2924/15311 , H01L2924/18161
Abstract: An electronic device includes a first and a second integrated-circuit chip that are stacked at a distance from one another, and a plurality of electrical connection pillars and at least one protective barrier interposed between the chips. The protective barrier delimits a free space between mutually opposing local regions of the chips, and an encapsulation block extends around the chip that has the smaller mounting face and over the periphery of the mounting face of the other chip. The electrical connection pillars and the protective barrier are made of at least one identical metallic material with a view to simultaneous fabrication.
Abstract translation: 电子设备包括彼此间隔地堆叠的第一和第二集成电路芯片，以及插入在芯片之间的多个电连接柱和至少一个保护屏障。 保护屏障限定了芯片的相互相对的局部区域之间的自由空间，并且封装块围绕具有较小安装面的芯片延伸，并且在另一芯片的安装面的周边上延伸。 电连接柱和保护屏障由至少一种相同的金属材料制成，以同时制造。
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公开(公告)号：US08975104B2
公开(公告)日：2015-03-10
申请号：US14185160
申请日：2014-02-20
Inventor： Mourad El-Gamal , Frederic Nabki , Paul-Vahe Cicek
CPC classification number: B81C1/00666 , B81B3/0021 , B81B7/008 , B81B2201/01 , B81B2201/0235 , B81B2201/0271 , B81B2201/03 , B81B2207/015 , B81B2207/03 , B81C1/00063 , B81C1/00246 , B81C1/00396 , B81C1/00587 , B81C2201/014 , B81C2201/0169 , B81C2201/0174 , B81C2203/0721 , B81C2203/0735
Abstract: A method of providing microelectromechanical structures (MEMS) that are compatible with silicon CMOS electronics is provided. The method providing for processes and manufacturing sequences limiting the maximum exposure of an integrated circuit upon which the MEMS is manufactured to below 350° C., and potentially to below 250° C., thereby allowing direct manufacturing of the MEMS devices onto electronics, such as Si CMOS circuits. The method further providing for the provisioning of MEMS devices with multiple non-conductive structural layers such as silicon carbide separated with small lateral gaps. Such silicon carbide structures offering enhanced material properties, increased environmental and chemical resilience while also allowing novel designs to be implemented taking advantage of the non-conductive material of the structural layer. The use of silicon carbide being beneficial within the formation of MEMS elements such as motors, gears, rotors, translation drives, etc where increased hardness reduces wear of such elements during operation.
Abstract translation: 提供了一种提供与硅CMOS电子器件兼容的微机电结构（MEMS）的方法。 该方法提供了将MEMS制造的集成电路的最大曝光限制在低于350℃并可能低于250℃的工艺和制造顺序，从而允许将MEMS器件直接制造到电子器件上，例如 作为Si CMOS电路。 该方法进一步提供具有多个非导电结构层的MEMS器件，例如用小的侧向间隙分离的碳化硅。 这种碳化硅结构提供了增强的材料性能，增加了环境和化学弹性，同时还允许利用结构层的非导电材料实现新颖的设计。 在形成MEMS元件（例如马达，齿轮，转子，平移驱动器等）中使用碳化硅是有益的，其中增加的硬度降低了操作期间这些元件的磨损。
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Patent Agency Ranking
公开(公告)号：US11906727B2
公开(公告)日：2024-02-20
申请号：US16761294
申请日：2018-08-02
Applicant: HAMAMATSU PHOTONICS K.K.
Inventor： Tatsuya Sugimoto , Tomofumi Suzuki , Kyosuke Kotani , Yutaka Kuramoto , Daiki Suzuki
CPC classification number: G02B26/0841 , B81C1/00555 , G02B7/1821 , G02B26/105 , H02N1/008 , B81B2201/042 , B81C2201/013 , B81C2201/0174 , B81C2201/0198
Abstract: A method for manufacturing an optical device includes: preparing a semiconductor substrate that includes a portion corresponding to a base, a movable unit, and an elastic support portion; forming a first resist layer in a region corresponding to the base on a surface of a first semiconductor layer which is opposite to an insulating layer; forming a depression in the first semiconductor layer by etching the first semiconductor layer using the first resist layer as a mask; forming a second resist layer in a region corresponding to a rib portion on a bottom surface of the depression, a side surface of the depression, and the surface of the first semiconductor layer which is opposite to the insulating layer; and forming the rib portion by etching the first semiconductor layer until reaching the insulating layer using the second resist layer as a mask.
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公开(公告)号：US11693230B2
公开(公告)日：2023-07-04
申请号：US16762174
申请日：2018-09-04
Applicant: HAMAMATSU PHOTONICS K.K.
Inventor： Tatsuya Sugimoto , Tomofumi Suzuki , Kyosuke Kotani
CPC classification number: G02B26/0841 , B81C1/00555 , G02B7/1821 , G02B26/105 , H02N1/008 , B81B2201/042 , B81C2201/013 , B81C2201/0174 , B81C2201/0198
Abstract: In an optical device, when viewed from a first direction, first, second, third, and fourth movable comb electrodes are respectively disposed between a first support portion and a first end of a movable unit, between a second support portion and a second end of the movable unit, between a third support portion and the first end, and between a fourth support portion and the second end of the movable unit. The first and second support portions respectively include first and second rib portions formed so that the thickness of each of the first and second support portions becomes greater than the thickness of the first torsion bar. The third and fourth support portions respectively include third and fourth rib portions formed so that the thickness of each of the third and fourth support portions becomes greater than the thickness of the second torsion bar.
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公开(公告)号：US09890040B2
公开(公告)日：2018-02-13
申请号：US14533947
申请日：2014-11-05
Applicant: Texas Instruments Incorporated
Inventor： YungShan Chang , Ricky A. Jackson , Jeff W. Ritchison , Neng Jiang
CPC classification number: B81C1/00523 , B81B3/0021 , B81B3/0072 , B81B7/02 , B81C1/00349 , B81C2201/0174 , G02B13/14 , G02B26/06
Abstract: An apparatus includes a lens material forming a lens. The apparatus also includes a piezoelectric capacitor over the lens material, where the piezoelectric capacitor is configured to change a shape of the lens material in response to a voltage across the piezoelectric capacitor to thereby change a focus of the lens. The apparatus further includes at least one stress compensation ring over a portion of the lens material and over at least a portion of the piezoelectric capacitor. The at least one stress compensation ring is configured to at least partially reduce bending of the lens material caused by stress on or in the lens material.
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公开(公告)号：WO2010003228A1
公开(公告)日：2010-01-14
申请号：PCT/CA2009/000931
申请日：2009-07-08
Applicant: THE ROYAL INSTITUTION FOR THE ADVANCEMENT OF LEARNING/MCGIII UNIVERSITY , EL-GAMAL, Mourad , CICEK, Paul-Vahé , NABKI, Frederic
Inventor： EL-GAMAL, Mourad , CICEK, Paul-Vahé , NABKI, Frederic
CPC classification number: B81C1/00666 , B81B3/0021 , B81B7/008 , B81B2201/01 , B81B2201/0235 , B81B2201/0271 , B81B2201/03 , B81B2207/015 , B81B2207/03 , B81C1/00063 , B81C1/00246 , B81C1/00396 , B81C1/00587 , B81C2201/014 , B81C2201/0169 , B81C2201/0174 , B81C2203/0721 , B81C2203/0735
Abstract: A method of providing microelectromechanical structures (MEMS) that are compatible with silicon CMOS electronics is provided. The method providing for processes and manufacturing sequences limiting the maximum exposure of an integrated circuit upon which the MEMS is manufactured to below 35O°C, and potentially to below 25O°C, thereby allowing direct manufacturing of the MEMS devices onto electronics, such as Si CMOS circuits. The method further providing for the provisioning of MEMS devices with multiple non-conductive structural layers such as silicon carbide separated with small lateral gaps. Such silicon carbide structures offering enhanced material properties, increased environmental and chemical resilience whilst also allowing novel designs to be implemented taking advantage of the non-conductive material of the structural layer. The use of silicon carbide being beneficial within the formation of MEMS elements such as motors, gears, rotors, translation drives, etc where increased hardness reduces wear of such elements during operation.
Abstract translation: 提供了一种提供与硅CMOS电子器件兼容的微机电结构（MEMS）的方法。 该方法提供了将MEMS制造的集成电路的最大曝光限制在低于350℃并可能低于250℃的工艺和制造顺序，从而允许将MEMS器件直接制造到电子器件上，例如Si CMOS电路。 该方法进一步提供具有多个非导电结构层的MEMS器件，例如用小的侧向间隙分离的碳化硅。 这种碳化硅结构提供增强的材料性能，增加环境和化学弹性，同时还允许利用结构层的非导电材料来实现新颖的设计。 在形成MEMS元件（例如马达，齿轮，转子，平移驱动器等）中使用碳化硅是有益的，其中增加的硬度降低了操作期间这些元件的磨损。
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公开(公告)号：JP4102158B2
公开(公告)日：2008-06-18
申请号：JP2002310314
申请日：2002-10-24
Applicant: 富士通株式会社
CPC classification number: B81C1/00182 , B81B2201/0235 , B81B2201/033 , B81B2201/042 , B81C2201/014 , B81C2201/0174 , G02B26/0841
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