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    Polarization defined zero misalignment vias for semiconductor packaging
    302.
    发明授权
    Polarization defined zero misalignment vias for semiconductor packaging 有权

    公开(公告)号：US11264239B2

    公开(公告)日：2022-03-01

    申请号：US16535618

    申请日：2019-08-08

    Applicant: Intel Corporation

    Inventor： Hiroki Tanaka ,  Aleksandar Aleksov ,  Sri Ranga Sai Boyapati ,  Robert A. May ,  Kristof Darmawikarta

    IPC: H01L21/027 ,  H01L23/00 ,  H01L23/485

    Abstract: Techniques that can assist with fabricating a semiconductor package that includes a zero misalignment-via (ZMV) and/or a trace formed using a polarization process are described. The disclosed techniques can result in creation of ZMVs and/or traces between the ZMVs using a process comprising application of polarized light to one or more resist layers (e.g., a photoresist layer, etc.). One embodiment of a technique includes modulating an intensity of light applied to one or more resist layers by interaction of a light source with a photomask and at least one polarizer such that one or more patterns are created on the one or more resist layers. One embodiment of another technique includes creating patterns on one or more resist layers with different types of polarized light formed from a photomask and at least one polarizer. The disclosed techniques can assist with reducing manufacturing costs, reducing development time, and increasing I/O density.

    INTERCONNECTION STRUCTURE FABRICATION USING GRAYSCALE LITHOGRAPHY
    304.
    发明申请
    INTERCONNECTION STRUCTURE FABRICATION USING GRAYSCALE LITHOGRAPHY 有权

    公开(公告)号：US20210343635A1

    公开(公告)日：2021-11-04

    申请号：US17375360

    申请日：2021-07-14

    Applicant: Intel Corporation

    Inventor： Johanna Swan ,  Henning Braunisch ,  Aleksandar Aleksov ,  Shawna Liff ,  Brandon Rawlings ,  Veronica Strong

    IPC: H01L23/498 ,  G03F1/38 ,  G03F1/54 ,  G03F1/68

    Abstract: An lithographic reticle may be formed comprising a transparent substrate, a substantially opaque mask formed on the transparent substrate that defines at least one exposure window, wherein the at least one exposure window has a first end, a first filter formed on the transparent substrate within the at least one exposure window and abutting the first end thereof, and a second filter formed on the transparent substrate within the at least one exposure window and abutting the first filter, wherein an average transmissivity of the first filter is substantially one half of a transmissivity of the second filter. In another embodiment, the at least one exposure window includes a third filter abutting the second end and is adjacent the second filter. Further embodiments of the present description include interconnection structures and systems fabricated using the lithographic reticle.

    INORGANIC DIES WITH ORGANIC INTERCONNECT LAYERS AND RELATED STRUCTURES
    307.
    发明申请
    INORGANIC DIES WITH ORGANIC INTERCONNECT LAYERS AND RELATED STRUCTURES 有权

    公开(公告)号：US20210296175A1

    公开(公告)日：2021-09-23

    申请号：US17338296

    申请日：2021-06-03

    Applicant: Intel Corporation

    Inventor： Aleksandar Aleksov ,  Feras Eid ,  Telesphor Kamgaing ,  Georgios Dogiamis ,  Johanna M. Swan

    IPC: H01L21/768 ,  H01L23/00

    Abstract: Disclosed herein are methods to fabricate inorganic dies with organic interconnect layers and related structures and devices. In some embodiments, an integrated circuit (IC) structure may be formed to include an inorganic die and one or more organic interconnect layers on the inorganic die, wherein the organic interconnect layers include an organic dielectric. An example method includes forming organic interconnect layers over an inorganic interconnect substrate and forming passive components in the organic interconnect layer. The organic interconnect layers comprise a plurality of conductive metal layers through an organic dielectric material. The plurality of conductive metal layers comprises electrical pathways. the passive components are electrically coupled to the electrical pathways.

    MICROELECTRONIC PACKAGE WITH MOLD-INTEGRATED COMPONENTS
    308.
    发明申请
    MICROELECTRONIC PACKAGE WITH MOLD-INTEGRATED COMPONENTS 有权

    公开(公告)号：US20210233856A1

    公开(公告)日：2021-07-29

    申请号：US17229991

    申请日：2021-04-14

    Applicant: Intel Corporation

    Inventor： Georgios Dogiamis ,  Aleksandar Aleksov ,  Feras Eid ,  Telesphor Kamgaing ,  Johanna M. Swan

    IPC: H01L23/538 ,  B81B7/00 ,  H01L23/28 ,  H01L23/552 ,  H01L21/56

    Abstract: Embodiments may relate to a microelectronic package that includes an overmold material, a redistribution layer (RDL) in the overmold material, and a die in the overmold material electrically coupled with the RDL on an active side of the die. The RDL is configured to provide electrical interconnection within the overmold material and includes at least one mold interconnect. The microelectronic package may also include a through-mold via (TMV) disposed in the overmold material and electrically coupled to the RDL by the mold interconnect. In some embodiments, the microelectronics package further includes a surface mount device (SMD) in the overmold material. The microelectronics package may also include a substrate having a face on which the overmold is disposed.

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