公开(公告)号：US20250112085A1

公开(公告)日：2025-04-03

申请号：US18375244

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Ziyin Lin ,  Haobo Chen ,  Yiqun Bai ,  Kyle Arrington ,  Jose Waimin ,  Ryan Carrazzone ,  Hongxia Feng ,  Dingying Xu ,  Srinivas Pietambaram ,  Minglu Liu ,  Seyyed Yahya Mousavi ,  Xinyu Li ,  Gang Duan ,  Wei Li ,  Bin Mu ,  Mohit Gupta ,  Jeremy Ecton ,  Brandon C. Marin ,  Xiaoying Guo ,  Ashay Dani

IPC: H01L21/762 ,  H01L21/768 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

Abstract: An apparatus is provided which comprises: a plurality of interconnect layers within a substrate, organic dielectric material over the plurality of interconnect layers, copper pads on a surface of a cavity within the organic dielectric material, an integrated circuit bridge device coupled with the copper pads, wherein a surface of the integrated circuit bridge device is elevated above an opening of the cavity, underfill material between the integrated circuit bridge device and the surface of the cavity, and build-up layers formed over the organic dielectric material around the integrated circuit bridge device. Other embodiments are also disclosed and claimed.

公开(公告)号：US20250105074A1

公开(公告)日：2025-03-27

申请号：US18977572

申请日：2024-12-11

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Haobo Chen ,  Wei Wei ,  Jose Fernando Waimin Almendares ,  Ryan Joseph Carrazzone ,  Kyle Jordan Arrington ,  Ziyin Lin ,  Dingying Xu ,  Hongxia Feng ,  Yiqun Bai ,  Hiroki Tanaka ,  Brandon Christian Marin ,  Jeremy Ecton ,  Benjamin Taylor Duong ,  Gang Duan ,  Srinivas Venkata Ramanuja Pietambaram ,  Rui Zhang ,  Mohit Gupta

IPC: H01L23/15 ,  H01L23/00 ,  H01L23/13 ,  H01L23/498

Abstract: Glass cores including protruding through glass vias and related methods are disclosed herein. An example substrate disclosed herein includes a glass core including a surface and a copper through glass via (TGV) extending through the glass core, the TGV including a protrusion extending from the surface.

公开(公告)号：US20240219660A1

公开(公告)日：2024-07-04

申请号：US18089934

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Hongxia Feng ,  Haobo Chen ,  Yiqun Bai ,  Dingying Xu ,  Eric J.M. Moret ,  Robert Alan May ,  Srinivas Venkata Ramanuja Pietambaram ,  Tarek A. Ibrahim ,  Gang Duan ,  Xiaoying Guo ,  Ziyin Lin ,  Bai Nie ,  Kyle Jordan Arrington ,  Bin Mu

IPC: G02B6/42 ,  G02B5/10

CPC classification number: G02B6/4246 ,  G02B5/10 ,  G02B6/4274

Abstract: A semiconductor device and associated methods are disclosed. In one example, the electronic device includes a photonic die and a glass substrate. In selected examples, the semiconductor device includes one or more turning mirrors to direct an optical signal between the photonic die and the glass substrate. Configurations of turning mirrors are provided to improve signal integrity and manufacturability.

公开(公告)号：US20240219655A1

公开(公告)日：2024-07-04

申请号：US18089916

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Haobo Chen ,  Bohan Shan ,  Bai Nie ,  Brandon C. Marin ,  Dingying Xu ,  Gang Duan ,  Hongxia Feng ,  Jeremy D. Ecton ,  Kristof Darmawikarta ,  Kyle Jordan Arrington ,  Srinivas Venkata Ramanuja Pietambaram ,  Xiaoying Guo ,  Yiqun Bai ,  Ziyin Lin

IPC: G02B6/42 ,  H01L21/48

CPC classification number: G02B6/4214 ,  H01L21/4803 ,  H01L23/49827

Abstract: A semiconductor device and associated methods are disclosed. In one example, the electronic device includes a photonic die and a glass substrate. In selected examples, the semiconductor device includes one or more turning mirrors to direct an optical signal between the photonic die and the glass substrate. Configurations of turning mirrors are provided to improve signal integrity and manufacturability.

公开(公告)号：US20240186227A1

公开(公告)日：2024-06-06

申请号：US18061181

申请日：2022-12-02

Applicant: Intel Corporation

Inventor： Haobo Chen ,  Bohan Shan ,  Kyle J. Arrington ,  Kristof Darmawikarta ,  Gang Duan ,  Jeremy D. Ecton ,  Hongxia Feng ,  Xiaoying Guo ,  Ziyin Lin ,  Brandon Christian Marin ,  Srinivas V. Pietambaram ,  Dingying Xu

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/538 ,  H01L23/64 ,  H01L25/065 ,  H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H05K1/18 ,  H05K3/46

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/642 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0655 ,  H05K1/0271 ,  H05K1/0306 ,  H05K1/113 ,  H05K1/181 ,  H05K3/4605 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15174 ,  H01L2924/157 ,  H01L2924/15788 ,  H05K2201/0195

Abstract: In one embodiment, an integrated circuit package substrate includes a core layer comprising a plurality of metal vias electrically coupling a first side of the core layer and a second side of the core layer opposite the first side. The package substrate further includes a build-up layer on the first side of the core layer, the build-up layer comprising metal vias within a dielectric material and electrically connected to the metal vias of the core layer. The dielectric material includes Silicon, Oxygen, and at least one of Boron or Phosphorus.

公开(公告)号：US20240128181A1

公开(公告)日：2024-04-18

申请号：US18047033

申请日：2022-10-17

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Brandon C. Marin ,  Srinivas V. Pietambaram ,  Hiroki Tanaka ,  Haobo Chen

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/14 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/145 ,  H01L23/49822 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L25/0655 ,  H01L24/32 ,  H01L2924/15311

Abstract: Embodiments of a microelectronic assembly that includes: a package substrate comprising a plurality of layers of organic dielectric material and conductive traces alternating with conductive vias in alternate layers of the organic dielectric material; and a plurality of integrated circuit dies coupled to a first side of the package substrate by interconnects, in which: the plurality of layers of the organic dielectric material comprises at least a first layer having a conductive via and a second layer having a conductive trace in contact with the conductive via, the second layer is not coplanar with the first layer, sidewalls of the conductive via are orthogonal to the conductive trace, and two opposing sidewalls of the conductive via separated by a width of the conductive via protrude from respectively proximate edges of the conductive trace by a protrusion that is at least ten times less than the width of the conductive via.

公开(公告)号：US20240114622A1

公开(公告)日：2024-04-04

申请号：US17956338

申请日：2022-09-29

Applicant: Intel Corporation

Inventor： Kristof Darmawikarta ,  Srinivas Venkata Ramanuja Pietambaram ,  Tarek A. Ibrahim ,  Cary Kuliasha ,  Siddharth K. Alur ,  Jung Kyu Han ,  Beomseok Choi ,  Russell K. Mortensen ,  Andrew Collins ,  Haobo Chen ,  Brandon C. Marin

IPC: H05K1/18 ,  H01L23/498 ,  H01L23/538 ,  H01L23/64 ,  H01L25/065 ,  H05K3/00 ,  H05K3/46

CPC classification number: H05K1/185 ,  H01L23/49822 ,  H01L23/5389 ,  H01L23/645 ,  H01L25/0655 ,  H05K3/0047 ,  H05K3/4644 ,  H05K2201/1003 ,  H05K2201/10674

Abstract: An electronic device includes a substrate including a core layer; a cavity formed in the core layer, wherein the cavity includes sidewalls plated with a conductive material; a prefabricated passive electronic component disposed in the cavity; and a cavity sidewall connection providing electrical continuity from the plated cavity sidewalls to a first surface of the substrate and to a second surface of the substrate.

公开(公告)号：US20240006298A1

公开(公告)日：2024-01-04

申请号：US17855040

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Steve Cho ,  Marcel Arlan Wall ,  Onur Ozkan ,  Ali Lehaf ,  Yi Yang ,  Jason Scott Steill ,  Gang Duan ,  Brandon C. Marin ,  Jeremy D. Ecton ,  Srinivas Venkata Ramanuja Pietambaram ,  Haifa Hariri ,  Bai Nie ,  Hiroki Tanaka ,  Kyle Mcelhinny ,  Jason Gamba ,  Venkata Rajesh Saranam ,  Kristof Darmawikarta ,  Haobo Chen

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49894 ,  H01L23/49816 ,  H01L21/4853 ,  H01L21/481 ,  H01L23/49838

Abstract: An electronic device may include an integrated circuit, for instance a semiconductor die. The electronic device may include a substrate having a first layer and a second layer. The first and second layers may include interconnects recessed below a surface of the substrate. The substrate may include a passivation layer directly coupled with portions of the interconnects. A solder resist material may at least partially cover portions of the passivation layer directly coupled with the first interconnect surface.

公开(公告)号：US20210391264A1

公开(公告)日：2021-12-16

申请号：US16902959

申请日：2020-06-16

Applicant: Intel Corporation

Inventor： Bai Nie ,  Kristof Kuwawi Darmawikarta ,  Srinivas V. Pietambaram ,  Haobo Chen ,  Gang Duan ,  Jason M. Gamba ,  Omkar G. Karhade ,  Nitin A. Deshpande ,  Tarek A. Ibrahim ,  Rahul N. Manepalli ,  Deepak Vasant Kulkarni ,  Ravindra Vijay Tanikella

IPC: H01L23/538 ,  H01L21/48

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

公开(公告)号：US20250125307A1

公开(公告)日：2025-04-17

申请号：US18985540

申请日：2024-12-18

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Jason M. Gamba ,  Brandon C. Marin ,  Srinivas V. Pietambaram ,  Xiaoxuan Sun ,  Omkar G. Karhade ,  Xavier Francois Brun ,  Yonggang Li ,  Suddhasattwa Nad ,  Bohan Shan ,  Haobo Chen ,  Gang Duan

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/538

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface, in a first layer; a redistribution layer (RDL) on the first layer, wherein the RDL includes conductive vias having a greater width towards a first surface of the RDL and a smaller width towards an opposing second surface of the RDL; wherein the first surface of the RDL is electrically coupled to the second surface of the first die by first solder interconnects having a first solder; and a second die in a second layer on the RDL, wherein the second die is electrically coupled to the RDL by second solder interconnects having a second solder, wherein the second solder is different than the first solder.