公开(公告)号：US20040053435A1

公开(公告)日：2004-03-18

申请号：US10601470

申请日：2003-06-23

Applicant: Matsushita Electric Industrial Co., Ltd.

Inventor： Kimiya Ikushima ,  Hiroyoshi Komobuchi ,  Mikiya Uchida

IPC: H01L021/00

CPC classification number: G01J5/20 ,  B81B3/0072 ,  B81B2201/0207 ,  B81B2203/0127 ,  B81C1/00047 ,  B81C1/00801 ,  B81C2201/0109 ,  B81C2201/014 ,  G01F1/6845 ,  G01J5/023 ,  G01J5/024 ,  G01J5/045 ,  G01J5/10 ,  G01J5/34

Abstract: A method for fabricating an electronic device includes the steps of: preparing a cavity defining sacrificial layer, at least the upper surface of which is covered with an etch stop layer; forming at least one first opening in the etch stop layer, thereby partially exposing the surface of the cavity defining sacrificial layer; etching the cavity defining sacrificial layer through the first opening, thereby defining a provisional cavity under the etch stop layer and a supporting portion that supports the etch stop layer thereon; and etching away a portion of the etch stop layer, thereby defining at least one second opening that reaches the provisional cavity through the etch stop layer and expanding the provisional cavity into a final cavity.

Abstract translation: 一种制造电子器件的方法包括以下步骤：制备限定牺牲层的空腔，其至少其上表面被蚀刻停止层覆盖; 在蚀刻停止层中形成至少一个第一开口，从而部分地暴露限定牺牲层的空腔的表面; 蚀刻通过所述第一开口限定牺牲层的所述腔，从而在所述蚀刻停止层下方限定临时空腔，以及在其上支撑所述蚀刻停止层的支撑部分; 并且蚀刻掉蚀刻停止层的一部分，从而限定通过蚀刻停止层到达临时腔的至少一个第二开口，并将临时空腔膨胀成最终空腔。

公开(公告)号：US06689694B1

公开(公告)日：2004-02-10

申请号：US09715446

申请日：2000-11-17

Applicant: Dong-Il Cho ,  Sangwoo Lee ,  Sangjun Park

Inventor： Dong-Il Cho ,  Sangwoo Lee ,  Sangjun Park

IPC: H01L21311

CPC classification number: C30B29/06 ,  B81B2203/0109 ,  B81B2203/0118 ,  B81C1/00801 ,  B81C2201/0132 ,  B81C2201/0133 ,  B81C2201/014 ,  C30B33/00

Abstract: Disclosed is a micromechanical system fabrication method using (111) single crystalline silicon as a silicon substrate and employing a reactive ion etching process in order to pattern a microstructure that will be separated from the silicon substrate and a selective release-etching process utilizing an aqueous alkaline solution in order to separate the microstructure from the silicon substrate. According to the micromechanical system fabrication method of the present invention, the side surfaces of microstructures can be formed to be vertical by employing the RIE technique. Furthermore, the microstructures can be readily separated from the silicon substrate by employing the selective release-etching technique using slow etching {111} planes as the etch stop in an aqueous alkaline solution. In addition, etched depths can be adjusted during the RIE step, thereby adjusting the thickness of the microstructure and the spacing between the microstructure and the silicon substrate.

Abstract translation: 公开了一种使用（111）单晶硅作为硅衬底并采用反应离子蚀刻工艺以便将从硅衬底分离的微结构图案和利用碱性水溶液的选择性剥离蚀刻工艺的微机械系统制造方法 溶液以将微结构与硅衬底分离。 根据本发明的微机械系统制造方法，通过采用RIE技术，可以将微结构的侧面形成为垂直的。 此外，通过使用选择性剥离蚀刻技术，通过使用慢蚀刻{111}晶面作为碱性水溶液中的蚀刻停止，微结构可以容易地与硅衬底分离。 此外，可以在RIE步骤期间调整蚀刻深度，从而调整微结构的厚度和微结构与硅衬底之间的间隔。

公开(公告)号：US20030197176A1

公开(公告)日：2003-10-23

申请号：US10128368

申请日：2002-04-22

Applicant: Glimmerglass Networks, Inc.

Inventor： James P. Spallas ,  Andres Fernandez ,  Thomas DeBey ,  Lawrence P. Muray

IPC: H01L029/04

CPC classification number: B81C1/00119 ,  B81B2201/042 ,  B81C2201/0104 ,  B81C2201/014 ,  B81C2201/017 ,  B81C2201/019

Abstract: Method for fabricating ultrathin gaps producing ultrashort standoffs in array structures includes sandwiching a patterned device layer between a silicon standoff layer and a silicon support layer, providing that the back surfaces of the respective silicon support layer and the standoff layer are polished to a desired thickness corresponding to the desired standoff height on one side and to at least a minimum height for mechanical strength on the opposing side, as well as to a desired smoothness. Standoffs and mechanical supports are then fabricated by etching to produce voids with the dielectric oxides on both sides of the device layer serving as suitable etch stops. Thereafter, the exposed portions of the oxide layers are removed to release the pattern, and a package layer is mated with the standoff voids to produce a finished device. The standoff layer can be fabricated to counteract curvature.

Abstract translation: 用于制造在阵列结构中产生超短距离的超薄间隙的方法包括在硅隔离层和硅支撑层之间夹着图案化的器件层，条件是相应的硅支撑层和支座层的背面被抛光到相应的所需厚度 达到一侧上所需的间隔高度，并且至少在相对侧上的机械强度的最小高度以及期望的平滑度。 然后通过蚀刻制造支座和机械支撑件以产生空隙，其中装置层两侧的电介质氧化物用作合适的蚀刻停止点。 此后，去除氧化物层的暴露部分以释放图案，并且将封装层与间隙空隙配合以产生成品装置。 可以制造隔离层以抵消曲率。

公开(公告)号：US06617657B1

公开(公告)日：2003-09-09

申请号：US09710326

申请日：2000-11-09

Applicant: Jun J. Yao ,  Robert J. Anderson

Inventor： Jun J. Yao ,  Robert J. Anderson

IPC: H01L2982

CPC classification number: B81C1/00484 ,  B81B2203/0118 ,  B81C2201/0108 ,  B81C2201/014 ,  B81C2201/019

Abstract: The present invention relates to a fabrication process relating to a fabrication process for manufacture of micro-electromechanical (MEM) devices such as cantilever supported beams. This fabrication process requires only two lithographic masking steps and offers moveable electromechanical devices with high electrical isolation. A preferred embodiment of the process uses electrically insulating glass substrate as the carrier substrate and single crystal silicon as the MEM component material. The process further includes deposition of an optional layer of insulating material such as silicon dioxide on top of a layer of doped silicon grown on a silicon substrate. The silicon dioxide is epoxy bonded to the glass substrate to create a silicon-silicon dioxide-epoxy-glass structure. The silicon is patterned using anisotropic plasma dry etching techniques. A second patterning then follows to pattern the silicon dioxide layer and an oxygen plasma etch is performed to undercut the epoxy film and to release the silicon MEM component. This two-mask process provides single crystal silicon MEMs with electrically isolated MEM component. Retaining silicon dioxide insulating material in selected areas mechanically supports the MEM component.

Abstract translation: 本发明涉及涉及用于制造诸如悬臂支撑梁的微机电（MEM）装置的制造工艺的制造工艺。 该制造工艺仅需要两个光刻掩模步骤，并提供具有高电绝缘性的可移动机电装置。 该方法的优选实施方案使用电绝缘玻璃基材作为载体基材，将单晶硅用作MEM组分材料。 该方法还包括在硅衬底上生长的掺杂硅层上沉积绝缘材料如二氧化硅的任选层。 二氧化硅是环氧键合到玻璃基底上以产生硅 - 二氧化硅 - 环氧玻璃结构。 使用各向异性等离子体干蚀刻技术将硅图案化。 然后进行第二图案化以对二氧化硅层进行图案化，并且执行氧等离子体蚀刻以切割环氧树脂膜并释放硅MEM组分。 该双掩模工艺提供具有电隔离的MEM组分的单晶硅MEM。 在选定区域保持二氧化硅绝缘材料机械地支撑MEM部件。

公开(公告)号：US20030138986A1

公开(公告)日：2003-07-24

申请号：US10268257

申请日：2002-10-09

Inventor： Mike Bruner

IPC: H01L021/00

CPC classification number: B81C1/00484 ,  B81B2201/0271 ,  B81B2203/0136 ,  B81C1/00246 ,  B81C1/00333 ,  B81C2201/0109 ,  B81C2201/014 ,  B81C2203/0136 ,  B81C2203/0735

Abstract: The current invention provides for encapsulated release structures, intermediates thereof and methods for their fabrication. The multi-layer structure has a capping layer, that preferably comprises silicon oxide and/or silicon nitride, and which is formed over an etch resistant substrate. A patterned device layer, preferably comprising silicon nitride, is embedded in a sacrificial material, preferably comprising polysilicon, and is disposed between the etch resistant substrate and the capping layer. Access trenches or holes are formed in to capping layer and the sacrificial material are selectively etched through the access trenches, such that portions of the device layer are release from sacrificial material. The etchant preferably comprises a noble gas fluoride NGF2x (wherein NgnullXe, Kr or Ar: and where xnull1, 2 or 3). After etching that sacrificial material, the access trenches are sealed to encapsulate released portions the device layer between the etch resistant substrate and the capping layer. The current invention is particularly useful for fabricating MEMS devices, multiple cavity devices and devices with multiple release features.

Abstract translation: 本发明提供了包封的释放结构，其中间体及其制备方法。 多层结构具有覆盖层，其优选地包括氧化硅和/或氮化硅，并且其形成在耐蚀刻衬底上。 优选地包括氮化硅的图案化器件层嵌入牺牲材料中，优选地包括多晶硅，并且设置在耐蚀刻衬底和覆盖层之间。 进入沟槽或孔形成在覆盖层中，并且牺牲材料通过进入沟槽被选择性地蚀刻，使得器件层的部分从牺牲材料释放。 蚀刻剂优选包含惰性气体氟化物NGF2x（其中Ng = Xe，Kr或Ar：其中x = 1,2或3）。 在蚀刻该牺牲材料之后，进入沟槽被密封以将器件层的释放部分封装在耐蚀刻衬底和覆盖层之间。 本发明对于制造具有多个释放特征的MEMS器件，多腔器件和器件特别有用。

公开(公告)号：US20030068838A1

公开(公告)日：2003-04-10

申请号：US09975125

申请日：2001-10-09

Inventor： Jin-shown Shie ,  Ji-cheng Lin ,  Chune-te Lin ,  Chih-tang Peng ,  Shih-han Yu ,  Kuo-ning Chiang

IPC: H01L021/00 ,  H01L029/82

CPC classification number: B81C1/00182 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81C2201/014 ,  B81C2201/016 ,  G01L9/0054

Abstract: The invention is a silicon pressure micro-sensing device and the fabrication process thereof. The silicon pressure micro-sensing device includes a pressure chamber, and is constituted of a P-type substrate with a taper chamber and an N-type epitaxial layer thereon. On the N-type epitaxial layer are a plurality of piezo-resistance sensing units which sense deformation caused by pressure. The fabrication pressure of the silicon pressure micro-sensing device includes a step of first making a plurality of holes on the N-type epitaxial layer to reach the P-type substrate beneath. Then, by an anisotropic etching stop technique, in which etchant pass through the holes, a taper chamber is formed in the P-type substrate. Finally, an insulating material is applied to seal the holes, thus attaining the silicon pressure micro-sensing device that is able to sense pressure differences between two ends thereof.

Abstract translation: 本发明是一种硅压力微型感测装置及其制造方法。 硅压力微型感测装置包括压力室，由具有锥形室的P型衬底和其上的N型外延层构成。 在N型外延层上是感测由压力引起的变形的多个压电感测单元。 硅压力微型感测装置的制造压力包括首先在N型外延层上制造多个孔以到达下面的P型衬底的步骤。 然后，通过各向异性蚀刻停止技术，其中蚀刻剂穿过孔，在P型衬底中形成锥形室。 最后，施加绝缘材料以密封孔，从而获得能够感测其两端之间的压力差的硅压力微检测装置。

公开(公告)号：US06544898B2

公开(公告)日：2003-04-08

申请号：US09891105

申请日：2001-06-25

Applicant: Bruce Polson ,  Nan Zhang ,  Howard P. Wilson

Inventor： Bruce Polson ,  Nan Zhang ,  Howard P. Wilson

IPC: H01L2100

CPC classification number: B81C1/00873 ,  B81C2201/014

Abstract: A microelectromechanical (MEMS) device and a method of fabricating a MEMS device are provided. The method of fabricating the MEMS device includes the steps of: etching a die release trench in a primary handle layer of a wafer having the handle layer, an etch-stop layer disposed on the primary handle layer, and a device layer disposed on the etch-stop layer; patterning a release trench in the device layer that is aligned with the release trench in the primary handle layer; temporarily attaching an additional handle layer to the primary handle layer; etching the device layer to define a structure in the device layer; removing the etch-stop layer; and removing the additional handle layer to release the die.

Abstract translation: 提供了一种微机电（MEMS）器件和MEMS器件的制造方法。 制造MEMS器件的方法包括以下步骤：蚀刻具有手柄层的晶片的主手柄层中的裸片释放沟槽，设置在主手柄层上的蚀刻停止层以及设置在蚀刻上的器件层 停留层 图案化在与主手柄层中的释放沟槽对准的器件层中的释放沟槽; 临时附加手柄层到主手柄层; 蚀刻器件层以限定器件层中的结构; 去除蚀刻停止层; 并移除附加手柄层以释放模具。

公开(公告)号：US06479315B1

公开(公告)日：2002-11-12

申请号：US09724514

申请日：2000-11-27

Applicant: Andrew J. Zosel ,  Peter M. Gulvin ,  Jingkuang Chen ,  Joel A. Kubby ,  Chuang-Chia Lin ,  Alex T. Tran

Inventor： Andrew J. Zosel ,  Peter M. Gulvin ,  Jingkuang Chen ,  Joel A. Kubby ,  Chuang-Chia Lin ,  Alex T. Tran

IPC: H01L2100

CPC classification number: B81C1/00666 ,  B81B2203/058 ,  B81C2201/014 ,  B81C2201/0164 ,  B81C2201/056 ,  G02B26/0833

Abstract: The present invention provides a micromechanical or microoptomechanical structure. The structure is produced by a process comprising defining a structure on a single crystal silicon layer separated by an insulator layer from a substrate layer; depositing and etching a polysilicon layer on the single crystal silicon layer, with remaining polysilicon forming mechanical or optical elements of the structure; exposing a selected area of the single crystal silicon layer; and releasing the formed structure.

Abstract translation: 本发明提供一种微机械或微机电结构。 该结构通过包括在衬底层上限定由绝缘体层分离的单晶硅层上的结构的方法制造; 沉积和蚀刻单晶硅层上的多晶硅层，剩余的多晶硅形成结构的机械或光学元件; 暴露单晶硅层的选定区域; 并释放形成的结构。

公开(公告)号：US06458615B1

公开(公告)日：2002-10-01

申请号：US09409570

申请日：1999-09-30

Applicant: Gary K. Fedder ,  Xu Zhu

Inventor： Gary K. Fedder ,  Xu Zhu

IPC: H01L2100

CPC classification number: H01L21/3065 ,  B81C1/00246 ,  B81C2201/014 ,  B81C2203/0742 ,  B81C2203/075 ,  G01P15/0802 ,  G01P15/125 ,  G01P2015/084

Abstract: A method for fabricating a micromachined structure. The method includes forming a circuitry layer having an upper etch-resistant layer on an upper surface of a substrate, directionally etching a portion of the circuitry layer exposed by the upper etch-resistant layer, and directionally etching a portion the substrate exposed by the upper etch-resistant layer with a deep reactive ion etch.

Abstract translation: 一种制造微加工结构的方法。 该方法包括在衬底的上表面上形成具有上耐蚀刻层的电路层，定向地蚀刻由上部耐蚀刻层暴露的电路层的一部分，并定向蚀刻由上部 具有深反应离子蚀刻的耐蚀刻层。

公开(公告)号：US06355498B1

公开(公告)日：2002-03-12

申请号：US09637069

申请日：2000-08-11

Applicant: Edward Chan ,  Harold Alexis Huggins ,  Jungsang Kim ,  Hyongsok Soh

Inventor： Edward Chan ,  Harold Alexis Huggins ,  Jungsang Kim ,  Hyongsok Soh

IPC: H01L2100

CPC classification number: H03H9/173 ,  B81B2201/0271 ,  B81C1/00142 ,  B81C2201/014 ,  H03H3/02 ,  H03H2003/021

Abstract: A new bulk resonator may be fabricated by a process that is readily incorporated in the traditional fabrication techniques used in the fabrication of monolithic integrated circuits on a wafer. The resonator is decoupled from the wafer by a cavity etched under the resonator using selective etching through front openings (vias) in a resonator membrane. In a typical structure the resonator is formed over a silicon wafer by first forming a first electrode, coating a piezoelectric layer over both the electrode and the wafer surface and forming a second electrode opposite the first on the surface of the piezoelectric layer. After this structure is complete, a number of vias are etched in the piezoelectric layer exposing the surface under the piezoelectric layer to a selective etching process that selectively attacks the surface below the piezoelectric layer creating a cavity under the resonator.

Abstract translation: 新的体谐振器可以通过容易地结合在晶片上制造单片集成电路中的传统制造技术中的工艺来制造。 谐振器通过使用谐振膜内的前开口（通孔）进行选择性蚀刻而在谐振器下方蚀刻的腔体与晶片分离。 在典型的结构中，谐振器通过首先形成第一电极而在硅晶片上形成，在电极和晶片表面上涂覆压电层，并形成与压电层表面上的第一电极相对的第二电极。 在该结构完成之后，在将压电层下方的表面暴露的压电层中蚀刻多个通孔至选择性蚀刻工艺，该选择性蚀刻工艺选择性地攻击压电层下方的表面，从而在谐振器下形成空腔。