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公开(公告)号：JP2013122878A
公开(公告)日：2013-06-20
申请号：JP2011271328
申请日：2011-12-12
Inventor： MIURA SHIGENORI
IPC: H01B13/00
Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a flat cable whose arc-like shape of a cross section is difficult to be deformed.SOLUTION: The method is for manufacturing a flat cable comprising a first insulating material, a second insulating material, and a conductor coated with the first insulating material and the second insulating material, and having concave on one side and convex on the other side by forming a cross section in the direction perpendicular to the length direction into an arc shape. The method includes the steps of: preparing a first precursor having the conductor formed on any one surface of the first insulating material; forming a second precursor by coating the surface, on which the conductor of the first precursor is formed, with the second insulating material so as to coat the conductor, and drying or heat treating the second insulating material adding tension in a length direction of the second precursor.
Abstract translation: 要解决的问题：提供一种扁平电缆的制造方法，其扁平电缆的截面形状难以变形。 解决方案：该方法用于制造扁平电缆，该扁平电缆包括第一绝缘材料，第二绝缘材料和涂覆有第一绝缘材料和第二绝缘材料的导体，并且在一侧具有凹形并且在另一侧上凸起 通过在垂直于长度方向的方向上形成一个圆弧形状的横截面。 该方法包括以下步骤：制备具有形成在第一绝缘材料的任何一个表面上的导体的第一前体; 通过将形成有第一前体的导体的表面涂覆在第二绝缘材料上形成第二前体，以涂覆导体，并且干燥或热处理在第二绝缘材料的长度方向上增加张力的第二绝缘材料 前体 版权所有（C）2013，JPO＆INPIT
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公开(公告)号：JP2010062372A
公开(公告)日：2010-03-18
申请号：JP2008227038
申请日：2008-09-04
Inventor： MIURA SHIGENORI
IPC: H05K3/46
CPC classification number: H05K3/4644 , H05K3/386 , H05K3/426 , H05K3/4602 , H05K3/4673 , H05K2201/09881
Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a multilayer laminated circuit board wherein a production efficiency is improved and the disconnection of a metallic circuit is hard to occur. SOLUTION: The method of manufacturing a multilayer laminated circuit board includes: a first step to form a through via penetrating a first resin film in the first resin film; a second step to form a metallic circuit on both front and rear surfaces and the inner wall surface of the through via of the first resin film; a third step to stack a second resin film on one or both surfaces of the front and rear surfaces of the first resin film wherein the metallic film is formed; and a fourth step to conduct the same operation as the first and second steps for the second resin film stacked in the third step. COPYRIGHT: (C)2010,JPO&INPIT
Abstract translation: 要解决的问题：提供一种制造多层叠电路板的方法，其中提高了生产效率并且难以发生金属电路的断开。 解决方案：制造多层叠层电路板的方法包括：第一步骤，形成穿过第一树脂膜中的第一树脂膜的通孔; 第二步骤，在第一树脂膜的前后表面和通孔的内壁表面上形成金属电路; 第三步骤，在形成有金属膜的第一树脂膜的前表面和后表面的一个或两个表面上堆叠第二树脂膜; 以及进行与第三步骤中堆叠的第二树脂膜的第一和第二步骤相同的操作的第四步骤。 版权所有（C）2010，JPO＆INPIT
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公开(公告)号：JP2009181736A
公开(公告)日：2009-08-13
申请号：JP2008017889
申请日：2008-01-29
Inventor： MIURA SHIGENORI
IPC: H01B5/14 , G02F1/1343 , H01M14/00
CPC classification number: G02F1/1345 , G02F2001/13629 , H01L27/3279 , H01L27/329 , H01L2251/308 , H05K3/24 , H05K2201/0108 , H05K2201/0326 , H05K2201/0338
Abstract: PROBLEM TO BE SOLVED: To provide an electrode substrate that strikes a balance between transparency and conductivity. SOLUTION: The electrode substrate is made up by forming a first conductive layer made of a first conductive material and a second conductive layer made of a second conductive material on a transparent base material. The first conductive layer is formed on the transparent base material, and the second conductive layer is formed on the transparent base material so as to cover at least part of the first conductive layer, with a width of the second conductive layer of 1.5 or more and 300 or less, provided that of the first conductive layer is 1. Although the second conductive material has a higher light transmittance than the first conductive material, it has a lower conductivity. COPYRIGHT: (C)2009,JPO&INPIT
Abstract translation: 要解决的问题：提供在透明度和电导率之间达到平衡的电极基板。 解决方案：电极基板通过在透明基材上形成由第一导电材料制成的第一导电层和由第二导电材料制成的第二导电层构成。 第一导电层形成在透明基材上，第二导电层形成在透明基材上，以便覆盖第一导电层的至少一部分，第二导电层的宽度为1.5以上， 300以下，只要第一导电层为1.虽然第二导电材料具有比第一导电材料更高的透光率，但其具有较低的导电性。 版权所有（C）2009，JPO＆INPIT
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Patent Agency Ranking
公开(公告)号：JP2005232484A
公开(公告)日：2005-09-02
申请号：JP2004039806
申请日：2004-02-17
Inventor： MIURA SHIGENORI
CPC classification number: H01L2224/11462 , H01L2224/11502 , H01L2224/11849 , H01L2224/11901 , H01L2224/1146
Abstract: PROBLEM TO BE SOLVED: To provide a low cost terminal in which the prevention in the production of whiskers and satisfactory solderability at a low temperature are made to coexist, and a surface coating layer is made thin and uniform. SOLUTION: In the terminal, an Sn layer is formed on the whole face or a part of an electrically conductive substrate, and an Sn alloy layer is formed on the Sn layer. The Sn layer is the one with a thickness of 0.1 to 20 μm composed of Sn and formed by electroplating. The Sn alloy layer is the one with a thickness of 0.1 to 20 μm composed of Sn and formed by electroplating. The Sn alloy layer is the one with a thickness of 0.1 to 20 μ composed of any one selected from an Sn-Ag binary alloy, an Sn-Ag-Cu ternary alloy, and an Sn-Ag-Cu-Bi quarternary alloy and formed by electroplating. COPYRIGHT: (C)2005,JPO&NCIPI
Abstract translation: 要解决的问题：提供一种低成本的终端，其中防止在晶须的生产和低温下的令人满意的可焊性共存，并且使表面涂层变得薄而均匀。 解决方案：在端子中，在整个表面或导电基板的一部分上形成Sn层，并且在Sn层上形成Sn合金层。 Sn层是由Sn构成的厚度为0.1〜20μm的电镀层，通过电镀形成。 Sn合金层是由Sn构成的厚度为0.1〜20μm的电镀形成的层。 Sn合金层是选自Sn-Ag二元合金，Sn-Ag-Cu三元合金和Sn-Ag-Cu-Bi三元合金中的任一种的厚度为0.1〜20μm的Sn合金层，形成 通过电镀。 版权所有（C）2005，JPO＆NCIPI
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公开(公告)号：JP3641632B1
公开(公告)日：2005-04-27
申请号：JP2003346921
申请日：2003-10-06
Applicant: Fcm株式会社
Inventor： 茂紀 三浦
IPC: B32B15/08 , C23C4/02 , C23C14/02 , C23C14/14 , C23C14/20 , C23C14/34 , C23C14/56 , C23C18/16 , C23C18/22 , C23C28/00 , C23C28/02 , C25D5/02 , C25D5/10 , H05K1/00 , H05K1/02 , H05K1/03 , H05K3/00 , H05K3/14 , H05K3/38
CPC classification number: H05K3/381 , C23C4/02 , C23C14/028 , C23C14/20 , C23C14/562 , C23C18/1608 , C23C18/1612 , C23C18/204 , C25D5/024 , C25D5/10 , H05K1/0393 , H05K2203/092 , H05K2203/1545
Abstract: 【課題】 本発明の目的は、絶縁性基体と金属層とが高い密着性を有するとともにファインな回路の形成が可能となる導電性シートを提供することにある。
【解決手段】 本発明は、絶縁性基体の表面の少なくとも一部に金属層が形成されている導電性シートに関するものであって、上記絶縁性基体は長尺状のものでありその表面の少なくとも一部に対して陽イオンが照射されることによりその照射部分の表面粗さＲａ値が０．２〜２００ｎｍとなっており、かつその陽イオンが照射された部分に対して上記金属層がスパッタリング法または蒸着法により形成されていることを特徴とする導電性シートに関する。
【選択図】 図１-
公开(公告)号：JP2005085923A
公开(公告)日：2005-03-31
申请号：JP2003315131
申请日：2003-09-08
Inventor： MIURA SHIGENORI
CPC classification number: H01L21/4846 , H01L21/4864 , H05K3/108 , H05K3/381 , H05K3/388 , H05K3/423 , H05K3/426 , H05K2201/0154 , H05K2201/0355 , H05K2201/0394 , H05K2201/09509 , H05K2201/09563 , H05K2201/09609 , H05K2203/092 , Y10T29/49155 , Y10T29/49165 , Y10T428/24917
Abstract: PROBLEM TO BE SOLVED: To provide a conductive sheet having an improved adhesion between an insulating substrate and a conductive layer. SOLUTION: The conductive sheet includes the insulating substrate having one or more via holes. The via holes are fine holes extended through the insulating substrate. A ground conductive layer is formed by a sputtering or evaporation method on the whole surface of the insulating substrate including wall faces of the via holes, and a coating conductive layer is formed on the whole or part of the surface of the ground conductive layer, wherein the via holes are filled up with the coating conductive layer. COPYRIGHT: (C)2005,JPO&NCIPI
Abstract translation: 要解决的问题：提供一种在绝缘基板和导电层之间具有改善的粘附性的导电片。 导电片包括具有一个或多个通孔的绝缘基板。 通孔是延伸穿过绝缘基板的细孔。 在包括通孔的壁面的绝缘基板的整个表面上通过溅射或蒸发法形成接地导电层，并且在接地导电层的整个或部分表面上形成涂层导电层，其中 通孔填充有涂层导电层。 版权所有（C）2005，JPO＆NCIPI
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公开(公告)号：JP2005048201A
公开(公告)日：2005-02-24
申请号：JP2003203036
申请日：2003-07-29
Inventor： MIURA SHIGENORI
Abstract: PROBLEM TO BE SOLVED: To provide a terminal in which the surface layer is not peeled or eluted, and which has excellent inserting-extracting properties and contact resistance, and further combines heat resistance, corrosion resistance, high hardness or the like, to provide a component comprising the same, and to provide a product comprising the same.
SOLUTION: In the terminal, a ruthenium layer composed of ruthenium alone or an alloy comprising ruthenium is formed on the whole face of a part of a conductive substrate, and a platinum layer composed of platinum alone or an alloy comprising platinum is formed on the whole face or a part of the ruthenium layer.
COPYRIGHT: (C)2005,JPO&NCIPIAbstract translation: 要解决的问题：为了提供表面层不被剥离或洗脱的端子，并且具有优异的插入提取性能和接触电阻，并且还结合耐热性，耐腐蚀性，高硬度等， 以提供包含该组分的组分，并提供包含该组分的产物。 解决方案：在端子中，在导电基板的一部分的整个表面上形成由单独的钌组成的钌层或包含钌的合金，并且形成由铂单独的铂层或包含铂的合金 在整个面上或钌层的一部分。 版权所有（C）2005，JPO＆NCIPI
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公开(公告)号：JP2005032901A
公开(公告)日：2005-02-03
申请号：JP2003194858
申请日：2003-07-10
Inventor： MIURA SHIGENORI
IPC: H01L23/498 , H01Q1/38 , H05K1/11
CPC classification number: H01L23/49838 , H01L23/49827 , H01L2924/0002 , H01Q1/38 , H05K1/115 , H05K2201/0979 , H01L2924/00
Abstract: PROBLEM TO BE SOLVED: To provide a conductive sheet for making the improvement of the adhesion between an insulating base substance and a conductive layer compatible with the improvement of the fineness of a circuit pattern. SOLUTION: The conductive sheet directly forms the conductive layer on the front and rear faces of the insulating base substance, and is electrically connected to the conductive layer existing the other face through a through hole or a via hole opening a hole so that one or more conductive layer existing the front and rear faces penetrates the insulating base substance. At least one or more conductive layers not connected electrically to the other conductive layer on the same surface on the front and rear faces of the insulating substance are formed. In the corresponding part of the insulating base substance forming one or more conductive layers, the two or more through hole or the two or more via holes are formed. COPYRIGHT: (C)2005,JPO&NCIPI
Abstract translation: 要解决的问题：提供一种用于提高绝缘基体和导电层之间的粘附性的导电片，其与电路图案的细度的提高相一致。 解决方案：导电片直接在绝缘基体的正面和背面形成导电层，并通过通孔或通孔打开孔与与另一面存在的导电层电连接，使得 存在前表面和后表面的一个或多个导电层渗透绝缘基体。 形成与绝缘物质的前表面和后表面上的相同表面上的另一导电层电连接的至少一个或多个导电层。 在形成一个或多个导电层的绝缘基体的相应部分中，形成两个或更多个通孔或两个或更多个通孔。 版权所有（C）2005，JPO＆NCIPI
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