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31.发明公开반도체 버퍼 구조체, 이를 포함하는 반도체 소자 및 반도체 버퍼 구조체를 이용한 반도체 소자 제조방법 有权半导体缓冲器结构，使用其的半导体器件以及使用半导体缓冲器结构制造半导体器件的方法
公开(公告)号：KR1020140021482A
公开(公告)日：2014-02-20
申请号：KR1020130088249
申请日：2013-07-25
Applicant: 삼성전자주식회사
IPC: H01L27/115 , G11C11/15
CPC classification number: H01L29/267 , G11C11/161 , H01L21/02104 , H01L21/02381 , H01L21/02458 , H01L21/02505 , H01L21/02507 , H01L21/0251 , H01L21/0254 , H01L29/2003 , H01L21/28273
Abstract: A disclosed method for manufacturing a semiconductor terminal includes a step of forming a buffer layer on a silicon substrate and a step of forming a nitride semiconductor layer on the buffer layer. The buffer layer includes a first layer which includes AlxInyGa1-x-yN (0
Abstract translation: 所公开的半导体端子的制造方法包括在硅衬底上形成缓冲层的步骤和在缓冲层上形成氮化物半导体层的步骤。 缓冲层包括第一层，其包括Al x In y Ga 1-x-y N（0≤x≤1,0<= y <=1,0,0≤x+y≤1），其中晶格常数为LP1， 小于硅衬底的晶格常数LP0; 第二层，其形成在第一层上并且包括Al x In y Ga 1-x-y N（0 <= x <1,0
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公开(公告)号：KR1020130031690A
公开(公告)日：2013-03-29
申请号：KR1020110095406
申请日：2011-09-21
Applicant: 삼성전자주식회사
IPC: H01L29/778 , H01L21/335
CPC classification number: H01L29/0649 , H01L29/2003 , H01L29/66462 , H01L29/7787
Abstract: PURPOSE: A power device and a method for manufacturing the same are provided to improve withstand voltage characteristic by using an electric field dispersion unit. CONSTITUTION: A nitride laminate(20) is formed on a substrate(10). A source electrode(S1), a drain electrode(D1) and a gate electrode(G1) are formed on the nitride laminate. An electric field dispersion unit(25) is formed in the rear surface or a part of the nitride laminate. A bonding metal layer includes a first bonding metal layer(15) and a second bonding metal layer(17).
Abstract translation: 目的：提供一种功率器件及其制造方法，以通过使用电场分散单元来提高耐压特性。 构成：在衬底（10）上形成氮化物层压体（20）。 在氮化物层压体上形成源电极（S1），漏电极（D1）和栅电极（G1）。 电场分散单元（25）形成在氮化物层压体的后表面或部分中。 接合金属层包括第一接合金属层（15）和第二接合金属层（17）。
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公开(公告)号：KR1020110061910A
公开(公告)日：2011-06-10
申请号：KR1020090118452
申请日：2009-12-02
Applicant: 삼성전자주식회사
CPC classification number: H01L33/60 , H01L33/007 , H01L33/10 , H01L33/382 , H01L33/387 , H01L33/405 , H01L33/46 , H01L2933/0016
Abstract: PURPOSE: A light emitting device and manufacturing method thereof are provided to have a reflecting layer embedded pattern, thereby increasing light emitting efficiency. CONSTITUTION: An uneven pattern includes a plurality of grooves and a mesa located between the grooves. A first reflective film(23) is included on a side of a groove. An n-type clad layer is placed on the uneven pattern. An active layer(35) is placed on the n-type clad layer. A p-type cladding layer is placed on the active layer. A first electrode is placed on one side of a substrate. A second electrode is placed on one side of the p-type cladding layer. A buffer layer(25) is placed on the mesa and the first reflective film.
Abstract translation: 目的：提供发光器件及其制造方法以具有反射层嵌入图案，从而提高发光效率。 构成：凹凸图案包括多个凹槽和位于凹槽之间的台面。 第一反射膜（23）包括在凹槽的一侧。 在不均匀图案上放置n型覆盖层。 有源层（35）被放置在n型覆层上。 p型包覆层放置在有源层上。 第一电极放置在基板的一侧。 第二电极放置在p型覆层的一侧。 缓冲层（25）放置在台面和第一反射膜上。
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公开(公告)号：KR1020110021406A
公开(公告)日：2011-03-04
申请号：KR1020090079189
申请日：2009-08-26
Applicant: 삼성전자주식회사
CPC classification number: H01L33/007 , B82Y20/00 , H01L33/0075 , H01L33/12 , H01L33/32 , H01L33/46 , H01L2933/0025 , Y10S977/893 , Y10S977/95
Abstract: PURPOSE: A light emitting apparatus and a manufacturing method thereof are provided to improve the light extraction efficiency by reducing the light absorption of a silicon substrate by comprising a reflective buffer layer including a distributed brag reflection layer. CONSTITUTION: A metallic buffer layer(132) is formed on a silicon substrate(110). A patterned distributed Brag reflector layer(134) is formed on the metallic buffer layer. The metallic buffer layer is patterned in the same pattern as the distributed Bragg reflector layer. An XY material layer(136) is formed on the patterned distributed Bragg reflector layer.
Abstract translation: 目的：提供一种发光装置及其制造方法，通过包括具有分散式吹塑反射层的反射缓冲层，通过降低硅衬底的光吸收来提高光提取效率。 构成：在硅衬底（110）上形成金属缓冲层（132）。 在金属缓冲层上形成图形分布的布拉格反射层（134）。 金属缓冲层以与分布式布拉格反射层相同的图案形成图案。 在图案化分布式布拉格反射层上形成XY材料层（136）。
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公开(公告)号：KR1020110018105A
公开(公告)日：2011-02-23
申请号：KR1020090075733
申请日：2009-08-17
Applicant: 삼성전자주식회사
IPC: H01L33/12
CPC classification number: H01L33/007 , H01L21/0237 , H01L21/02439 , H01L21/0254 , H01L21/02639 , H01L21/0265 , H01L27/156 , H01L33/0079 , H01L33/12 , H01L33/20
Abstract: PURPOSE: A substrate structure and a manufacturing method of the same are provided to prevent Si from being melt-back through Ga by oxidizing the surface of a substrate and a pattern region after forming the pattern region. CONSTITUTION: A substrate structure comprises a substrate(20) and a buffer layer(22) The buffer layer is formed on the substrate by a certain pattern. A buffer layer is supported by a substrate protrusion which is formed after the surface of the substrate is etched. The bottom of a buffer layer which is not contacted with the substrate protrusion is exposed to outside. A nitride semiconductor layer is formed through lateral growth which is rapider vertical growth.
Abstract translation: 目的：提供一种基板结构及其制造方法，用于通过在形成图案区域之后氧化基板的表面和图案区域来防止Si熔化回Ga。 构成：衬底结构包括衬底（20）和缓冲层（22）。缓冲层通过某种图案形成在衬底上。 缓冲层由衬底突出部支撑，该衬底突起在衬底的表面被蚀刻之后形成。 不与基板突起接触的缓冲层的底部暴露于外部。 通过横向生长形成氮化物半导体层，其是纵横向生长。
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Patent Agency Ranking
公开(公告)号：KR1020090081603A
公开(公告)日：2009-07-29
申请号：KR1020080007563
申请日：2008-01-24
Applicant: 삼성전자주식회사
IPC: H01L21/336 , H01L29/78 , B82Y40/00
CPC classification number: H01L29/0669 , H01L21/02603 , H01L29/0673
Abstract: A method for fabricating a self aligned three dimensional transistor is provided to limit the height of a gate by using a mask layer as a planarization stop layer in a planarization process. A mask having a shape of a source forming area, a drain forming area, and a channel forming area is formed on a substrate including a silicon layer on a first insulating layer. The silicon layer is patterned by the mask. The mask is etched on the channel forming area. An undercut is formed in the lower part of the channel forming area. A nano wire channel(118) is formed by thermally oxidizing the channel forming area. A gate oxide layer(160) is formed on the nano wire channel. A gate material covering the mask is deposited on the substrate. A gate is formed by planarizing the gate material using the mask as a CMP stop layer. The mask is removed. A source(115') and a drain(117') are formed by irradiating the impurity from the substrate.
Abstract translation: 提供一种用于制造自对准三维晶体管的方法，以在平坦化处理中通过使用掩模层作为平坦化停止层来限制栅极的高度。 在第一绝缘层上的包括硅层的基板上形成具有源极形成区域形状的掩模，漏极形成区域和沟道形成区域。 通过掩模对硅层进行图案化。 在通道形成区域上蚀刻掩模。 在通道形成区域的下部形成有底切。 通过热氧化通道形成区域形成纳米线通道（118）。 在纳米线通道上形成栅氧化层（160）。 覆盖掩模的栅极材料沉积在基板上。 通过使用掩模将栅极材料平坦化作为CMP停止层来形成栅极。 去除面具。 通过从衬底照射杂质形成源（115'）和漏极（117'）。
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公开(公告)号：KR1020090031114A
公开(公告)日：2009-03-25
申请号：KR1020070096962
申请日：2007-09-21
Applicant: 삼성전자주식회사
CPC classification number: H01L29/0665 , B82Y10/00 , H01L29/0673 , H01L29/161 , Y10S438/933 , Y10S977/747 , Y10S977/762 , Y10S977/938
Abstract: A nanowire formation method is provided to control easily size and forming location of nanowire and not to move Nanowire to another substrate in order to manufacture semiconductor device. A nanowire formation method comprises steps of: forming SiyGe1-y layer patterned on base layer; performing oxidation process for the patterned SiyGe1-y layer; and forming the oxide layer and nanowire. The step of forming the patterned SiyGe1-y layer includes steps of: preparing lamination structure comprising an insulating layer(10), an Si layer(20) and an SixGe1-x layer(SG1); diversifying the Si layer to the SiyGe1-y layer by performing the oxidation process for the SixGe1-x layer; and patterning the SiyGe1-y layer.
Abstract translation: 提供纳米线形成方法以便容易地控制纳米线的尺寸和形成位置，并且不将纳米线移动到另一基底上以便制造半导体器件。 纳米线形成方法包括以下步骤：形成在基底层上图案化的SiyGe1-y层; 对图案化的SiyGe1-y层进行氧化处理; 并形成氧化物层和纳米线。 形成图案化SiyGe1-y层的步骤包括以下步骤：制备包括绝缘层（10），Si层（20）和SixGe1-x层（SG1）的层压结构; 通过对SixGe1-x层进行氧化处理，将Si层分散到SiyGe1-y层; 并构图SiyGe1-y层。
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公开(公告)号：KR1020060128332A
公开(公告)日：2006-12-14
申请号：KR1020050049689
申请日：2005-06-10
Applicant: 삼성전자주식회사
Inventor： 김준연
IPC: H01S5/183
CPC classification number: H01S5/18397 , H01S5/06256 , H01S5/18366
Abstract: An electrically-pumped high power vertical cavity surface emitting laser is provided to obtain a high output in single mode by distributing uniformly carriers. An electrically-pumped high power vertical cavity surface emitting laser includes a first DBR mirror(20), an active layer(30) formed on the first DBR mirror, a second DBR mirror(40) formed on the active layer, and a capping layer(70) formed on the second DBR mirror. The second DBR mirror includes low refractive layers(41) of n number, a high refractive layer(43) inserted between the low refractive layers, and a carrier spreading layer inserted between the low refractive layers and the high refractive layer in order to distribute uniformly carriers.
Abstract translation: 提供电泵浦的高功率垂直腔表面发射激光器，以通过均匀载体分布来获得单模式的高输出。 电泵浦大功率垂直腔表面发射激光器包括第一DBR反射镜（20），形成在第一DBR反射镜上的有源层（30），形成在有源层上的第二DBR反射镜（40）和覆盖层 （70）形成在第二DBR镜上。 第二DBR镜包括n数的低折射层（41），插入在低折射层之间的高折射层（43）和插入在低折射层和高折射层之间的载流子扩散层，以均匀分布 载体。
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公开(公告)号：KR100594037B1
公开(公告)日：2006-06-30
申请号：KR1020040003694
申请日：2004-01-19
Applicant: 삼성전자주식회사
IPC: G02B6/14
CPC classification number: G02B6/1228 , H01S5/1014 , H01S5/1025 , H01S5/1064 , H01S5/2231 , H01S5/50
Abstract: 본 발명에 따른 반도체 기판과, 상기 반도체 기판 상에 성장된 하부 클래드와, 상기 하부 클래드 상에 성장된 상부 클래드로 이루어진 반도체 광소자는 광을 생성 및 증폭시키기 위해서 상기 하부 및 상부 클래드 사이에 성장된 활성층을 포함하는 이득 영역과, 상기 하부 및 상부 클래드 사이에 상기 활성층으로부터 연장되게 성장된 도파층을 포함함으로써 상기 이득 영역에서 생성된 상기 광의 모드 크기를 변환시켜서 출력하기 위한 광모드 크기 변환 영역을 포함하며, 상기 광모드 크기 변환 영역의 도파층은 상기 활성층으로부터 그 두께가 점차적으로 작아지게 성장되며, 상기 상부 클래드는 상기 이득 영역을 포함하는 상기 반도체 광소자의 일단으로부터 상기 광모드 크기 변환 영역을 포함하는 상기 반도체 광소자의 타단으로 갈수록 그 폭이 좁아지는 테이퍼 구조를 갖도록 식각된다.
광모드 변환, 반도체 광소자, 이득 영역-
公开(公告)号：KR100566212B1
公开(公告)日：2006-03-29
申请号：KR1020030081038
申请日：2003-11-17
Applicant: 삼성전자주식회사
IPC: H01L21/20
CPC classification number: C30B29/40 , C30B25/04 , H01L21/02392 , H01L21/02546 , H01L21/0262 , H01L21/02639
Abstract: 본 발명은 유기금속화학기상증착법에 의한 선택영역 성장방법에 관한 것이다.
본 발명은 (001) 결정면을 갖는 반도체 기판 위에 예정된 상기 선택영역의 폭보다 넓은 폭의 제1 윈도우를 갖는 제1 마스크 패턴과, 상기 제1 윈도우 가장자리에서의 상기 Ⅲ족 반도체 원료가스의 표면이동을 차단하는 차단영역을 형성하기 위한 제2 윈도우를 갖도록 상기 제1 마스크 패턴과 이격 배치되며 예정된 상기 선택영역의 폭과 동일한 폭의 제3 윈도우를 갖는 제2 마스크 패턴을 형성하는 과정과; 상기 제2 윈도우 및 제3 윈도우에 의해 노출된 상기 반도체 기판 위에 유기금속화학기상증착법에 의한 반도체 성장층을 성장하는 과정을 포함하여 이루어짐을 특징으로 한다.
선택영역 성장, 유기금속화학기상증착법, 표면 이동
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