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公开(公告)号：KR1020080097126A
公开(公告)日：2008-11-04
申请号：KR1020080024517
申请日：2008-03-17
Applicant: 삼성전자주식회사
CPC classification number: G11C13/0004 , G11C11/5678 , G11C13/004 , G11C13/0069 , G11C16/10 , G11C16/26
Abstract: A reading method of multi-level phase change memory device is provided to supply a recovery current to the selected memory cell before the sensing operation is performed, so the distribution of the memory cells having the amorphous state is recovered. A reading method of the multi-level phase change memory device including the memory cells having one among a plurality of data states is comprised of steps: recovering the selected memory cells so that each resistance of the memory cell is recovered to initial resistance regardless of a plurality of data states respectively(241a); sensing data from the selected memory cells(241b). The selected memory cells are recovered so that each initial resistance of a plurality of data state values is not changed.
Abstract translation: 提供了多级相变存储器件的读取方法，用于在执行感测操作之前向选择的存储单元提供恢复电流，从而恢复具有非晶状态的存储单元的分布。 包括具有多个数据状态之一的存储单元的多电平相变存储器件的读取方法包括以下步骤：恢复所选存储单元，使得存储单元的每个电阻恢复到初始电阻，而不管 多个数据状态（241a）; 感测来自所选存储单元（241b）的数据。 恢复所选择的存储单元，使得多个数据状态值的每个初始电阻不改变。
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公开(公告)号：KR1020080090864A
公开(公告)日：2008-10-09
申请号：KR1020070034246
申请日：2007-04-06
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L45/06 , H01L21/76897 , H01L45/1233 , H01L45/143 , H01L45/144
Abstract: A multi-bit phase transition memory device and a method for manufacturing the same are provided to implement a multi-bit phase transition memory element having small transition regions by storing multi-bit data corresponding to the number of phase transition patterns. A multi-bit phase transition memory device includes a first electrode(71), a second electrode(95) and a data storage(Rp). The first electrode is provided on a substrate(51). The second electrode is spaced apart from the first electrode. The data storage is disposed between the first electrode and the second electrode. The data storage has one or a plurality of intermediate electrodes(75) and a plurality of phase transition patterns. The data storage has a first phase transition pattern coming in contact with the first electrode, a second phase transition pattern coming in contact with the second electrode and the intermediate electrode interposed between the first phase transition pattern the second phase transition pattern.
Abstract translation: 提供了一种多位相变存储器件及其制造方法，用于通过存储对应于相变图案数量的多位数据来实现具有小过渡区域的多位相变存储元件。 多位相变存储器件包括第一电极（71），第二电极（95）和数据存储器（Rp）。 第一电极设置在基板（51）上。 第二电极与第一电极间隔开。 数据存储设置在第一电极和第二电极之间。 数据存储具有一个或多个中间电极（75）和多个相变图案。 数据存储器具有与第一电极接触的第一相变图案，与第二电极接触的第二相变图案和介于第一相变图案之间的第二相变图案的中间电极。
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公开(公告)号：KR1020080056969A
公开(公告)日：2008-06-24
申请号：KR1020060130218
申请日：2006-12-19
Applicant: 삼성전자주식회사
CPC classification number: H04N1/6027 , G06T5/007 , G06T2207/20016
Abstract: An apparatus and a method for enhancing picture quality of a color image by using Laplacian pyramid are provided to carry out brightness improvement of total image illumination by using a low resolution approximate image and to carry out local brightness contrast ratio improvement by using a band pass image, in order to increase saturation proper to the brightness value of the input image and to improve picture quality. A picture quality enhancing method comprises the steps of; extracting light and darkness data from a color image data(S20); generating low resolution image data and band pass image data, by using Laplacian pyramid from the light and darkness data; generating the global brightness improved image data by receiving the low resolution image data(S40); generating local contrast ratio improved image data by receiving the band pass image data(S50); and combining the global brightness improved image data with the local contrast ratio improved image data to generate the improved light and darkness data(S60).
Abstract translation: 提供一种通过使用拉普拉斯金字塔提高彩色图像的图像质量的装置和方法，以通过使用低分辨率近似图像来实现全图像照明的亮度改善，并且通过使用带通图像来实现局部亮度对比度改善 ，以增加适合于输入图像的亮度值的饱和度并提高图像质量。 图像质量增强方法包括以下步骤： 从彩色图像数据中提取亮度和暗度数据（S20）; 通过使用拉普拉斯金字塔从亮度和黑暗数据生成低分辨率图像数据和带通图像数据; 通过接收低分辨率图像数据生成全局亮度改善的图像数据（S40）; 通过接收带通图像数据产生局部对比度改善图像数据（S50）; 并且将全局亮度改善的图像数据与局部对比度比改善的图像数据组合以产生改进的亮度和黑暗数据（S60）。
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Patent Agency Ranking
公开(公告)号：KR1020080048708A
公开(公告)日：2008-06-03
申请号：KR1020060119028
申请日：2006-11-29
Applicant: 삼성전자주식회사
IPC: G02F1/1339
CPC classification number: G02F1/1339 , G02F1/136227 , G02F2201/123 , G02F2201/50 , H01L29/786
Abstract: An LCD(Liquid Crystal Display) and a manufacturing method thereof are provided to extend a passivation layer to a peripheral region for encompassing the outside of a display region and to form a concave portion within the extended passivation layer. A transparent panel includes a display area and a peripheral area. Plural pixel capacitors and plural TFT(Thin Film Transistor)s are arranged at the display area. A passivation layer(130) insulates the pixel capacitor and the TFT. A portion of the passivation layer is extended toward the peripheral area. A concave portion(131) is arranged within the passivation layer of the peripheral area. The transparent panel includes upper and lower substrates(200,100) including the display area and peripheral area. A sealing member(300) is arranged at the peripheral areas of the upper and lower substrates so that the upper and lower substrates are sealed. The concave portion is arranged within the passivation layer at the boundary surface of the display area(D) and the peripheral area(P).
Abstract translation: 提供LCD（液晶显示器）及其制造方法以将钝化层延伸到外围区域以包围显示区域的外部，并在延伸的钝化层内形成凹部。 透明面板包括显示区域和外围区域。 多个像素电容器和多个TFT（薄膜晶体管）被布置在显示区域。 钝化层（130）使像素电容器和TFT绝缘。 钝化层的一部分朝向周边区域延伸。 凹部（131）设置在周边区域的钝化层内。 透明面板包括包括显示区域和外围区域的上基板和下基板（200,100）。 密封构件（300）布置在上基板和下基板的周边区域处，使得上基板和下基板被密封。 凹部被布置在显示区域（D）和周边区域（P）的边界面处的钝化层内。
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公开(公告)号：KR1020080032517A
公开(公告)日：2008-04-15
申请号：KR1020060098459
申请日：2006-10-10
Applicant: 삼성전자주식회사
Abstract: A semiconductor memory cell having a recessed landing pad, and a method of fabricating the same are provided to prevent a metal silicide film and the second landing pad from being exposed during the process of forming node contact holes, by making upper surfaces of the metal silicide film and second landing pad have levels that are lower than that of the first landing pad, thereby preventing short-circuit between node contact plugs and second landing pad. A semiconductor memory cell having a recessed landing pad comprises a lower interlayer insulation film(120), the first landing pad(116), the second landing pad(118), an intermediate interlayer insulation film(122), a conductive line(133), and a metal silicide film(118s). The lower interlayer insulation film covers a semiconductor substrate(100). The first landing pad comes in contact with the semiconductor substrate by passing through the lower interlayer insulation film. The second landing pad has an upper surface whose level is lower than that of the first lading pad within the lower interlayer insulation film and comes in contact with the semiconductor substrate as being spaced away from the first landing pad. The intermediate interlayer insulation film covers the first landing pad and the lower interlayer insulation film. The conductive line is disposed on the intermediate interlayer insulation film and is electrically connected to the second landing pad as penetrating the lower interlayer insulation film and the intermediate interlayer insulation film. The metal silicide film is disposed between the second landing pad and the conductive line and has an upper surface whose level is lower than that of the first landing pad. The metal silicide film is covered by the lower interlayer insulation film.
Abstract translation: 提供一种具有凹陷的着陆垫的半导体存储单元及其制造方法，用于防止在形成节点接触孔的过程中金属硅化物膜和第二着陆焊盘暴露，通过使金属硅化物的上表面 胶片和第二着陆垫的水平低于第一着陆垫的水平，从而防止节点接触塞和第二着陆垫之间的短路。 具有凹入的着陆焊盘的半导体存储单元包括下层间绝缘膜（120），第一着陆焊盘（116），第二着陆焊盘（118），中间层间绝缘膜（122），导线（133） ，和金属硅化物膜（118s）。 下层间绝缘膜覆盖半导体衬底（100）。 第一着陆板通过下层间绝缘膜与半导体衬底接触。 第二着陆焊盘的上表面的水平低于下层间绝缘膜内的第一层焊盘的上表面，并且与半导体衬底接触，与第一着陆焊盘间隔开。 中间层间绝缘膜覆盖第一着陆焊盘和下层间绝缘膜。 导电线设置在中间层间绝缘膜上，并且穿透下层间绝缘膜和中间层间绝缘膜而电连接到第二着陆焊盘。 金属硅化物膜设置在第二着陆焊盘和导电线之间，并且具有的电平低于第一着陆焊盘的上表面。 金属硅化物膜被下层层间绝缘膜覆盖。
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公开(公告)号：KR1020070056862A
公开(公告)日：2007-06-04
申请号：KR1020050116006
申请日：2005-11-30
Applicant: 삼성전자주식회사
Inventor： 김형준
IPC: G06F12/00
Abstract: A memory structure and a memory corruption finding method for dynamically allocating a memory to a system program are provided to maximally prevent memory corruption which is cause of shutting down a system or an abnormal operation, and find a part causing the memory corruption from tasks in case that the memory corruption occurs in an RTOS. A memory allocating module dynamically allocates memory blocks according to a memory allocation request of the program. The memory block is divided into a header field(10) including more than one feature value for detecting the memory corruption, an actual data field(20) for storing actual data, and a trailer field(30) including the information of program corrupting the memory. The trailer field comprises a post-guard field(31) storing a post-guard value for detecting the memory corruption of the allocated memory block, a filename field(32) storing a file name of the program causing the memory corruption, a line number field(33) storing a line number of the program causing the memory corruption, and a task ID field(34) storing a task ID of the program causing the memory corruption.
Abstract translation: 提供了一种用于向系统程序动态分配存储器的存储器结构和存储器损坏查找方法，以最大限度地防止因关闭系统或异常操作而导致的内存损坏，并且发现导致内存损坏的部分 内存损坏发生在RTOS中。 存储器分配模块根据程序的存储器分配请求动态地分配存储器块。 存储器块被分成包括用于检测存储器损坏的多于一个特征值的头部字段（10），用于存储实际数据的实际数据字段（20）和包括程序破坏信息的程序的信息的尾部字段（30） 记忆。 预告字段包括：后保护字段（31），其存储用于检测所分配的存储器块的存储器损坏的后保护值;存储导致存储器损坏的程序的文件名的文件名字段（32） 存储导致存储器损坏的程序的行号的字段（33），以及存储导致存储器损坏的程序的任务ID的任务ID字段（34）。
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公开(公告)号：KR100678270B1
公开(公告)日：2007-02-01
申请号：KR1020000007477
申请日：2000-02-17
Applicant: 삼성전자주식회사
Inventor： 김형준
IPC: H04Q1/30
Abstract: 가. 청구범위에 기재된 발명이 속한 기술분야
전송 시스템의 데이터 베이스 구축 방법에 관한 기술이다.
나. 발명이 해결하고자 하는 기술적 과제
전송 시스템에서 초기화시 구성 데이터 베이스를 구축할 경우 빠르고, 시스템의 부하가 적도록 하기 위한 데이터 베이스 구축 방법을 제공한다.
다. 발명의 해결방법의 요지
본 발명은 메시지 타스크와 에이전트를 구분하여 구성한 전송 시스템에서 구성 데이터 베이스를 구축하는 방법으로, 초기 동작시 상기 에이전트가 상기 메시지 타스크를 생성하는 제1과정과, 생성할 구축 데이터 베이스에 따른 메시지 테이블을 생성하는 제2과정과, 상기 메시지 타스크는 상기 메시지 테이블에 초기화 메시지가 존재하는가를 검사하는 제3과정과, 상기 검사결과 초기화 메시지가 존재하는 경우 MCU로 전달하여 요구 메시지를 송신하고, 응답 신호를 수신하여 상기 에이전트 블록으로 전달하는 제4과정과, 상기 요구 메시지가 종료되면 이를 이용하여 상기 에이전트가 전송 시스템의 구성 데이터 베이스를 구축하는 제5과정으로 이루어짐을 특징으로 한다.
라. 발명의 중요한 용도
전송 시스템에서 구성 데이터 베이스를 구축하는데 사용된다.
전송 시스템, 데이터 베이스 구축, 구성 데이터 베이스. -
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