公开(公告)号：KR1019970003730B1

公开(公告)日：1997-03-21

申请号：KR1019930031608

申请日：1993-12-30

Applicant: 삼성전자주식회사

Inventor： 송준의

IPC: H01L21/70

CPC classification number: H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/15312 ,  H01L2924/00014 ,  H01L2924/00

Abstract: (a) The passivation layer(203) containing the opening part exposing the bonding pad(202) bare on the semiconductor substrate(201) is formed and the polyamide layer(204A) and the photoresist mask pattern(205) is formed in regular order thereon. (b) The bonding pad is exposed by selectively etching of the polyamide layer(204A), then the photoresist mask pattern is removed. (c) After the polyamide layer(206A) is formed on the overall surface, the photoresist mask pattern(207) is formed. (d) The bonding pad is bared by etching the polyamide layer(206A) selectively, then the photoresist mask pattern(207) is removed.

Abstract translation: （a）形成包含暴露在半导体衬底（201）上的接合焊盘（202）的开口部分的钝化层（203），聚酰胺层（204A）和光致抗蚀剂掩模图案（205）以规则顺序形成 在其上。 （b）通过选择性地蚀刻聚酰胺层（204A）来暴露接合焊盘，然后除去光致抗蚀剂掩模图案。 （c）在整个表面上形成聚酰胺层（206A）之后，形成光致抗蚀剂掩模图案（207）。 （d）通过选择性地蚀刻聚酰胺层（206A）来露出接合焊盘，然后去除光致抗蚀剂掩模图案（207）。

公开(公告)号：KR1019960042978A

公开(公告)日：1996-12-21

申请号：KR1019950013442

申请日：1995-05-26

Applicant: 삼성전자주식회사

Inventor： 이태정 ,  송준의

IPC: H01L21/30

Abstract: 접촉 저항을 감소시키고 도전층의 집적도를 증가시키기 위한 접촉 개구부의 장치 및 제조방법에 관해 개시한다. 본 발명은 반도체 장치의 기판에 형성된 제1도전층과 상기 제1도전층상에 형성된 절연층과 상기 절연층내에 형성되고 상기 제1도전층의 표면을 노출시키고 개구부 하단의 폭이 상단의 폭보다 넓은 접촉 개구부 및 상기 접촉 개구부의 내부 및 상기 절연층 상부에 침적 패터닝되어 제1도전층과 접촉하는 제2도전층을 구비하는 것을 특징으로 하는 반도체 장치로 이루어져 있다. 또한, 본 발명은 상기 접촉 개구부의 장치를 제조하는데 있어서, 가장 적합한 제조방법을 제공한다.
본 발명에 의하면 접촉 개구부 하단의 폭이 상단의 폭보다 넓기 때문에 제1도전층과 제2도전층과의 접촉시 접촉저항이 감소하게 되며 미스얼라인 여유도가 증가하게 되어 다층구조에서의 집적도가 증가한다.

公开(公告)号：KR1019950000144B1

公开(公告)日：1995-01-10

申请号：KR1019920000510

申请日：1992-01-15

Applicant: 삼성전자주식회사

Inventor： 송준의

IPC: H01L27/06 ,  H01L27/00 ,  H01L29/70

Abstract: The method comprises; (A) depositing an oxide film on whole surface of a wafer to form a spacer on side face of the gate region; (B) covering the only active base region of Bipolar transistor with photoresis; (C) removing the oxide layer existing on the active base region by etching; and (D) forming a source electrode, a gate and a drain of MOS transistor, and base, emitter and collector electrodes of Bipolar, and base, emitter and collector electrodes of Bipolar transistor. The method prevents the base region of Bipolar transistor from damaging.

Abstract translation: 该方法包括： （A）在晶片的整个表面上沉积氧化膜以在栅极区域的侧面上形成间隔物; （B）用光吸收覆盖双极晶体管的唯一活性碱基区域; （C）通过蚀刻去除存在于活性碱性区域上的氧化物层; 和（D）形成MOS晶体管的源电极，栅极和漏极以及双极晶体管的基极，发射极和集电极以及双极晶体管的基极，发射极和集电极。 该方法防止双极晶体管的基极区域损坏。

公开(公告)号：KR1019920020598A

公开(公告)日：1992-11-21

申请号：KR1019910005632

申请日：1991-04-09

Applicant: 삼성전자주식회사

Inventor： 김동준 ,  송준의

IPC: H01L27/06

Abstract: 내용 없음

公开(公告)号：KR1020120073394A

公开(公告)日：2012-07-05

申请号：KR1020100135146

申请日：2010-12-27

Applicant: 삼성전자주식회사

Inventor： 김선영 ,  송준의 ,  임태완

IPC: H01L21/28 ,  H01L21/8242 ,  H01L21/8247

CPC classification number: H01L21/76807 ,  H01L21/76831 ,  H01L27/11521 ,  H01L2221/1031

Abstract: PURPOSE: A semiconductor device and a manufacturing method thereof are provided to prevent conductive materials from remaining on an insulation film pattern in a connector manufacturing process by integrating a wire for transmitting a signal with a connector in contact with a contact area. CONSTITUTION: A through hole(301a,301b) exposes a contact area(CA) of a substrate(100). A first insulation film pattern(300) covers a conductive structure(200). A second insulation film pattern(400) includes a line-shaped trench(401a,401b) which is extended in a wiring direction. A connector(610) fills the through hole. A metal wire(620) fills the trench with the connector.

Abstract translation: 目的：提供一种半导体器件及其制造方法，用于通过将用于传输信号的电线与与接触区域接触的连接器集成来防止导电材料在连接器制造过程中保留在绝缘膜图案上。 构成：通孔（301a，301b）暴露基板（100）的接触区域（CA）。 第一绝缘膜图案（300）覆盖导电结构（200）。 第二绝缘膜图案（400）包括在布线方向上延伸的线状沟槽（401a，401b）。 连接器（610）填充通孔。 金属线（620）用连接器填充沟槽。

公开(公告)号：KR1020120020550A

公开(公告)日：2012-03-08

申请号：KR1020100084220

申请日：2010-08-30

Applicant: 삼성전자주식회사

Inventor： 유환배 ,  송준의 ,  신현철 ,  유다훈

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/11519 ,  H01L21/28273 ,  H01L27/11521 ,  H01L21/28141 ,  H01L21/7682 ,  H01L21/823425

Abstract: PURPOSE: A non-volatile memory device having an air gap on a common source line and a manufacturing method thereof are provided to remarkably reduce parasitic coupling capacitance between gate patterns by forming an impurity region of a line shape on a semiconductor substrate at a lower part of an air gap. CONSTITUTION: A first gate pattern(GP1) and a second gate pattern(GP2) are formed on a semiconductor substrate(1). The first gate pattern includes a first side wall and a second side wall. First insulating spacers and second insulating spacers are respectively formed on the first side walls and the second side walls. A capping dielectric layer(17) is formed on the front side of the semiconductor substrate including the first and second insulating spacers. An air gap(AG) is formed between the first and second gate patterns by selectively eliminating the first insulating spacers.

Abstract translation: 目的：提供一种在公共源极线上具有气隙的非易失性存储器件及其制造方法，通过在半导体衬底的下部形成线状杂质区域，显着降低栅极图案之间的寄生耦合电容 的气隙。 构成：在半导体衬底（1）上形成第一栅极图案（GP1）和第二栅极图案（GP2）。 第一栅极图案包括第一侧壁和第二侧壁。 分别在第一侧壁和第二侧壁上形成第一绝缘垫片和第二绝缘垫片。 在包括第一和第二绝缘间隔物的半导体衬底的前侧形成有覆盖电介质层（17）。 通过选择性地消除第一绝缘间隔件，在第一和第二栅极图案之间形成气隙（AG）。

公开(公告)号：KR1020030021652A

公开(公告)日：2003-03-15

申请号：KR1020010055017

申请日：2001-09-07

Applicant: 삼성전자주식회사

Inventor： 장형순 ,  김석규 ,  최준영 ,  안성식 ,  송준의

IPC: H01L27/11 ,  H01L21/8244

Abstract: PURPOSE: A unit cell of a static random access memory(SRAM) is provided to minimize a three dimension phenomenon by making transistors constituting the unit cell of the SRAM have a rectangular type, and to increase an operation speed by forming the unit cell whose width and length are similar. CONSTITUTION: The first and second active regions(310,320) are disposed in a straight line of a semiconductor substrate, crossing the center of the unit cell and separated from each other. The third and fourth active regions(330,340) are in parallel with the first and second active regions, disposed in the semiconductor substrate at both sides of the first and second active regions, respectively. An isolation layer pattern is disposed in a predetermined region of the semiconductor substrate to define the first, second, third and fourth active regions. The first and second gate electrodes(410,420) cross the first and third active regions and the second and fourth active regions, respectively. A word line(400) of a straight line type passes through a gap between the first and second gate electrodes and crosses the third and fourth active regions.

Abstract translation: 目的：提供静态随机存取存储器（SRAM）的单位单元，以通过使构成SRAM的单位晶体管的晶体管具有矩形类型来最小化三维现象，并且通过形成单位单元的宽度来增加操作速度， 长度相似。 构成：第一和第二有源区（310,320）设置在半导体衬底的直线上，与单元电池的中心相交并彼此分离。 第三和第四有源区域（330,340）分别与第一和第二有源区域平行地布置在第一和第二有源区域两侧的半导体衬底中。 隔离层图案设置在半导体衬底的预定区域中以限定第一，第二，第三和第四有源区。 第一和第二栅极电极（410,420）分别与第一和第三有源区域以及第二和第四有源区域交叉。 直线型的字线（400）通过第一和第二栅电极之间的间隙，并穿过第三和第四有源区。

公开(公告)号：KR1020030015703A

公开(公告)日：2003-02-25

申请号：KR1020010049585

申请日：2001-08-17

Applicant: 삼성전자주식회사

Inventor： 안성식 ,  송준의 ,  장형순 ,  이성태 ,  최준영

IPC: H01L21/3205

Abstract: PURPOSE: A structure of dielectric layer in multilevel interconnection and a manufacturing method thereof are provided to form an insulating spacer for filling an opening over-etched by mis-alignment during a photolithography process, thereby preventing short between adjacent wires. CONSTITUTION: A structure of dielectric layer in multilevel interconnection has a first interlayer dielectric film(130) and an etch stop film(140). A contact wire(160) is passed in turn through the first interlayer dielectric film(130) and the etch stop film(140). The contact wire(160) is connected to a first conductive film pattern on an upper portion of the etching prevention film(140). A third interlayer dielectirc film(130) covers the first conductive film and has an opening for exposing an upper surface of the first conductive film pattern at a desired region. An insulating film spacer covers a sidewall of the opening while exposing the first conductive film pattern. The exposed first conductive film pattern is connected to a second conductive film pattern on an upper portion of the third interlayer dielectric film(130).

Abstract translation: 目的：提供多层互连中的电介质层的结构及其制造方法，以在光刻工艺期间形成用于填充通过错误对准而被过蚀刻的开口的绝缘间隔物，从而防止相邻导线之间的短路。 构成：多层互连中的电介质层的结构具有第一层间绝缘膜（130）和蚀刻停止膜（140）。 接触线（160）依次通过第一层间电介质膜（130）和蚀刻停止膜（140）。 接触导线160连接到防腐蚀膜140的上部的第一导电膜图案。 第三层间绝缘膜（130）覆盖第一导电膜并且具有用于在期望区域暴露第一导电膜图案的上表面的开口。 绝缘膜间隔件在露出第一导电膜图案的同时覆盖开口的侧壁。 暴露的第一导电膜图案连接到第三层间电介质膜（130）的上部上的第二导电膜图案。

公开(公告)号：KR100319895B1

公开(公告)日：2002-01-10

申请号：KR1019990054789

申请日：1999-12-03

Applicant: 삼성전자주식회사

Inventor： 송준의

IPC: G11C11/414

CPC classification number: H01L27/11 ,  G11C11/412 ,  H01L27/1104 ,  Y10S257/909

Abstract: 완전씨모스에스램셀이제공된다. 이에스램셀은반도체기판에서로평행하게형성된제1 및제2 활성영역과, 제1 활성영역및 제2 활성영역사이의반도체기판에제1 활성영역과평행하게형성된제3 활성영역과, 제3 활성영역및 제2 활성영역사이의반도체기판에제2 활성영역과평행하게형성된제4 활성영역과, 제1 및제2 활성영역을가로지르는워드라인과, 제1 활성영역및 제3 활성영역을가로지르는제1 공통도전전극과, 제2 활성영역및 제4 활성영역을가로지르는제2 공통도전전극을포함한다.

公开(公告)号：KR1020010075946A

公开(公告)日：2001-08-11

申请号：KR1020000002901

申请日：2000-01-21

Applicant: 삼성전자주식회사

Inventor： 하회성 ,  송준의

IPC: H01L21/76

CPC classification number: H01L21/76897 ,  H01L21/76224

Abstract: PURPOSE: A borderless contact structure and a method for forming the structure are provided to increase the integrity of SRAMs and to improve standby current characteristic of the SRAM. CONSTITUTION: The borderless contact structure includes a device isolation layer(61), an impurity region(72), an etching stop spacer(96), an etching stop layer(73) and interlayer isolation layer(75) and a contact hole(77a). The device isolation layer is formed on the predetermined region of the semiconductor substrate(51) and includes a protrusion higher than the surface of the semiconductor substrate. The impurity region is formed on an active region between device isolation layers. The etching stop spacer is formed on a sidewall of the protrusion. The etching stop layer and interlayer isolation layer are sequentially accumulated on the impurity region, device isolation layer and the etching stop spacer. The contact hole penetrates the interlayer isolation layer and the etching stop layer and exposes the etching stop spacer adjacent to the impurity region and the impurity region.

Abstract translation: 目的：提供无边界接触结构和形成该结构的方法以增加SRAM的完整性并提高SRAM的待机电流特性。 构成：无边界接触结构包括器件隔离层（61），杂质区（72），蚀刻阻挡间隔物（96），蚀刻停止层（73）和层间隔离层（75）和接触孔 ）。 器件隔离层形成在半导体衬底（51）的预定区域上并且包括高于半导体衬底表面的突起。 在器件隔离层之间的有源区上形成杂质区。 蚀刻停止间隔件形成在突起的侧壁上。 蚀刻停止层和层间隔离层依次堆积在杂质区域，器件隔离层和蚀刻停止间隔物上。 接触孔穿透层间隔离层和蚀刻停止层，并使邻近杂质区域和杂质区域的蚀刻停止隔片露出。