公开(公告)号：KR1020090064927A

公开(公告)日：2009-06-22

申请号：KR1020070132311

申请日：2007-12-17

Applicant: 삼성전자주식회사

Inventor： 설종선 ,  신유철 ,  심재성

IPC: G11C16/00 ,  H01L21/8247 ,  H01L27/115

CPC classification number: H01L27/11568 ,  G11C16/3468 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L21/823493

Abstract: An integrated circuit memory device is provided, which eliminates the memory cells of heap strings connected to dummy bit lines. An integrated circuit memory device comprises the semiconductor substrate and memory cell array. The memory cell array has the first and the second NAND string(101). Each first and second NAND strings is comprised of charge trap memory cells. The first and the second dummy NAND strings(102) divide the first and second NAND strings. The second dummy NAND string is adjacent to the first heap NAND string.

Abstract translation: 提供一种集成电路存储器件，其消除了连接到虚拟位线的堆串的存储单元。 集成电路存储器件包括半导体衬底和存储单元阵列。 存储单元阵列具有第一和第二NAND串（101）。 每个第一和第二NAND串由电荷陷阱存储单元组成。 第一和第二虚拟NAND串（102）划分第一和第二NAND串。 第二个虚拟NAND串与第一堆NAND串相邻。

公开(公告)号：KR100655432B1

公开(公告)日：2006-12-08

申请号：KR1020050030458

申请日：2005-04-12

Applicant: 삼성전자주식회사

Inventor： 신유철 ,  최정달

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L27/115 ,  H01L27/11568

Abstract: 본 발명은 비휘발성 메모리 장치 및 제조방법을 제공한다.
본 발명의 제조방법에 의하면, 셀 영역, 고전압 영역, 저전압 영역을 갖는 반도체 기판에 있어서, 셀 영역과 고전압 영역의 소자분리막 일부를 노출시키는 마스크를 사용한다. 상기 마스크를 이용하면, 셀 영역에 문턱 전압 조절 불순물 이온을 주입하는 단계와 고전압 영역의 소자분리막에 채널 스톱 불순물 이온을 주입하는 단계 및 셀 영역에 저전압 게이트 도전막과 저전압 게이트 절연막을 제거하는 단계 등을 병합하여 진행할 수 있다.
한편, 상기한 제조 방법을 이용하여 제조되는 비휘발성 메모리 장치는 동작 특성이 향상된다. 즉, 상기 셀 영역과 고전압 영역의 소자분리막 일부를 노출시키는 마스크를 이용하여, 상기 마스크에 따라 노출되는 소자분리막을 리세스하고 여기에 게이트 도전막을 채우면, 고전압 영역에 형성되는 트랜지스터는 상기 리세스된 깊이 만큼 채널 폭이 증가되어 동작 특성이 향상될 수 있다.

公开(公告)号：KR100456700B1

公开(公告)日：2004-11-10

申请号：KR1020020061403

申请日：2002-10-09

Applicant: 삼성전자주식회사

Inventor： 신유철

IPC: H01L27/02

CPC classification number: H01L28/20 ,  H01L27/0629 ,  H01L27/10897 ,  H01L27/115 ,  H01L27/11531 ,  H01L27/11568 ,  Y10S257/904

Abstract: Disclosed is a semiconductor device with a resistor pattern and methods of fabricating the same. Embodiments of the present invention provide a method of fabricating a resistor pattern having high sheet resistance by using a polycide layer for a gate electrode in a semiconductor device with the resistor pattern. Embodiments of the invention also provide a semiconductor device with a resistor pattern that is formed narrower than the minimum line width that can be defined in a photolithographic process so that sheet resistance thereof increases, and a method of fabricating the same.

Abstract translation: 公开了一种具有电阻器图案的半导体器件及其制造方法。 本发明的实施例提供了一种通过在具有电阻器图案的半导体器件中使用用于栅电极的多晶硅硅化物层来制造具有高薄层电阻的电阻器图案的方法。 本发明的实施例还提供一种具有电阻器图案的半导体器件及其制造方法，所述电阻器图案形成为比可在光刻工艺中限定的最小线宽更窄，以使其薄层电阻增加。

公开(公告)号：KR100375235B1

公开(公告)日：2003-03-08

申请号：KR1020010013931

申请日：2001-03-17

Applicant: 삼성전자주식회사

Inventor： 신유철 ,  박종우 ,  최정달

IPC: H01L27/115 ,  H01L21/8247 ,  H01L29/788

CPC classification number: H01L27/11568 ,  H01L27/115 ,  H01L29/792

Abstract: A flash memory having a charge-storage dielectric layer. According to one embodiment, charge-storage dielectric layers are formed over the first and second active regions. The charge-storage layer over the first active region is not connected to the charge-storage layer over the second active region. A gate line overlies the charge-storage layer and extends across the first and second active regions and the isolation region. The charge-storage layer can be formed only where a gate line intersects an active region of a semiconductor substrate, not on an isolation region. Thus, undesirable influence or disturbance from adjacent memory cells can be avoided.

Abstract translation: 一种具有电荷存储介电层的闪存。 根据一个实施例，在第一和第二有源区上形成电荷存储电介质层。 第一有源区上的电荷存储层不连接到第二有源区上的电荷存储层。 栅极线覆盖电荷存储层并延伸穿过第一和第二有源区以及隔离区。 电荷存储层可以仅在栅极线与半导体衬底的有源区交叉而不在隔离区上形成。 因此，可以避免来自相邻存储单元的不希望的影响或干扰。

公开(公告)号：KR1020020073960A

公开(公告)日：2002-09-28

申请号：KR1020010013931

申请日：2001-03-17

Applicant: 삼성전자주식회사

Inventor： 신유철 ,  박종우 ,  최정달

IPC: H01L27/115 ,  H01L21/8247 ,  H01L29/788

CPC classification number: H01L27/11568 ,  H01L27/115 ,  H01L29/792

Abstract: PURPOSE: An SONOS(Silicon Oxide Nitride Oxide Semiconductor) flash memory device and a formation method thereof are provided to minimize interference between adjacent cells. CONSTITUTION: A semiconductor substrate(200) defined by a plurality of isolation regions(202a) and active regions(204) is prepared. A dielectric film(212) composed of a lower oxide(206), a nitride(208) and an upper oxide(210) is formed on the active regions(204) and is to be cross with a plurality of gate lines(214). A plurality of impurity diffusion regions(216a-216d) are formed in the active regions of both sides of the gate lines. The lower portion of the gate lines(214) is directly connected to the upper part of the isolation regions(202a).

Abstract translation: 目的：提供一种SONOS（氧化硅氮化物半导体）闪存器件及其形成方法，以最小化相邻单元之间的干扰。 构成：制备由多个隔离区域（202a）和有源区域（204）限定的半导体衬底（200）。 在有源区（204）上形成由低氧化物（206），氮化物（208）和上氧化物（210）组成的电介质膜（212），并与多条栅极线（214）交叉， 。 在栅极线的两侧的有源区域中形成有多个杂质扩散区域（216a〜216d）。 栅极线（214）的下部直接连接到隔离区（202a）的上部。

公开(公告)号：KR1020020073959A

公开(公告)日：2002-09-28

申请号：KR1020010013930

申请日：2001-03-17

Applicant: 삼성전자주식회사

Inventor： 임용식 ,  최정달 ,  곽홍석 ,  신유철

IPC: H01L21/8247

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11529 ,  H01L29/792

Abstract: PURPOSE: A non-volatile memory device having a structure of a MONOS gate and a method for fabricating the same are provided to optimize each structure of a selective transistor, a low voltage MOS transistor, a high voltage MOS transistor. CONSTITUTION: An isolation layer(3) is arranged on a predetermined region of a semiconductor substrate(1). The first well(5), the second well(7b), and a pocket well(7a) are arranged on the semiconductor substrate(1). The pocket well(7a) is surrounded by the first well(5). The second active region of the peripheral circuit region(b) is surrounded by the second well(7b). A conductive type dopant different from the semiconductor substrate(1) is doped on the first well(5). The same conductive type dopant as the semiconductor substrate(1) is doped on the pocket well(7a) and the second well(7b). Accordingly, the pocket well(7a) is electrically isolated from the semiconductor substrate(1). A high voltage gate pattern(24h) is formed on a predetermined region of the third active region. The high voltage gate pattern(24h) has a high voltage gate insulating layer(17) and a high voltage gate electrode(23h). A sidewall of the high voltage gate pattern(24h) is covered by a gate spacer(26b). A high voltage source/drain region(30h) is formed at both sides of the high voltage gate pattern(24h). A low voltage gate pattern(24l) including a lower voltage gate insulating layer(21) and a low voltage gate electrode(23l) is formed on a predetermined region of the second active region. A sidewall of the low voltage gate pattern(24l) is covered by the gate spacer(26b). A low voltage source/drain region(281) is formed at both sides of the low voltage gate pattern(24l). A cell gate pattern(24c) is formed on the first region of the first active region. The cell gate pattern(24c) is formed with a cell gate electrode(23c) and a cell gate insulating layer(14) including a tunnel oxide layer(9), a silicon nitride layer pattern(11), and an upper oxide layer pattern(13). A selective gate pattern(24s) including a selective gate insulating layer(21) and a selective gate electrode(23s) is formed on the second region of the first active region. A low density source/drain region(25) is formed on the first active region of the both sides of the selective gate pattern(24s) and the cell gate pattern(24c). A cell array region(a) is covered by a spacer insulating layer pattern(26a). The semiconductor substrate(1) is covered by an interlayer dielectric(31).

Abstract translation: 目的：提供具有MONOS栅极结构的非易失性存储器件及其制造方法，以优化选择晶体管，低电压MOS晶体管，高压MOS晶体管的每个结构。 构成：隔离层（3）布置在半导体衬底（1）的预定区域上。 第一阱（5），第二阱（7b）和口袋（7a）布置在半导体衬底（1）上。 口袋（7a）被第一孔（5）包围。 外围电路区域（b）的第二有源区域被第二阱（7b）包围。 与半导体衬底（1）不同的导电型掺杂剂掺杂在第一阱（5）上。 在凹穴（7a）和第二阱（7b）上掺杂与半导体衬底（1）相同的导电类型掺杂剂。 因此，口袋（7a）与半导体衬底（1）电隔离。 高电压栅极图案（24h）形成在第三有源区域的预定区域上。 高压栅极图案（24h）具有高压栅极绝缘层（17）和高压栅电极（23h）。 高压栅极图案（24h）的侧壁被栅极间隔物（26b）覆盖。 在高压栅极图案（24h）的两侧形成有高电压源极/漏极区域（30h）。 在第二有源区的预定区域上形成包括低电压栅极绝缘层（21）和低电压栅电极（23l）的低电压栅极图案（241）。 低压栅极图案（241）的侧壁被栅极间隔物（26b）覆盖。 在低压栅极图案（24l）的两侧形成有低压源极/漏极区域（281）。 单元栅极图案（24c）形成在第一有源区域的第一区域上。 单元栅极图案（24c）形成有单元栅电极（23c）和包括隧道氧化物层（9），氮化硅层图案（11）和上氧化物层图案的单元栅极绝缘层（14） （13）。 在第一有源区的第二区域上形成包括选择栅极绝缘层（21）和选择栅电极（23s）的选择栅极图案（24s）。 在选择栅极图案（24s）和单元栅极图案（24c）的两侧的第一有源区上形成低密度源极/漏极区（25）。 单元阵列区域（a）被间隔绝缘层图案（26a）覆盖。 半导体衬底（1）被层间电介质（31）覆盖。

公开(公告)号：KR1020020017220A

公开(公告)日：2002-03-07

申请号：KR1020000050419

申请日：2000-08-29

Applicant: 삼성전자주식회사

Inventor： 신유철

IPC: H01L21/76

CPC classification number: H01L21/823481 ,  H01L21/76229 ,  H01L21/76232

Abstract: PURPOSE: A trench isolation-type semiconductor device is provided to add a predetermined depth of a trench in an intermediate region of the trench when the trench having a sufficient depth is not formed in a trench isolation process. CONSTITUTION: At least two regions having different thickness of gate insulation layers are formed. The trench isolation-type semiconductor device has at least one curved trench where a silicon substrate(10) constituting the bottom surface of the trench has a step. The thickness difference of the gate insulation layer between the regions is more than 100 angstrom. The curved trench is formed only in a region where the gate insulation layer is more than 200 angstrom in thickness.

Abstract translation: 目的：提供沟槽隔离型半导体器件，以在沟槽隔离工艺中未形成具有足够深度的沟槽时，在沟槽的中间区域中增加沟槽的预定深度。 构成：形成具有不同厚度的栅极绝缘层的至少两个区域。 沟槽隔离型半导体器件具有至少一个弯曲沟槽，其中构成沟槽底表面的硅衬底（10）具有台阶。 区域之间的栅极绝缘层的厚度差大于100埃。 弯曲的沟槽仅在栅极绝缘层的厚度大于200埃的区域中形成。

公开(公告)号：KR1020010080841A

公开(公告)日：2001-08-25

申请号：KR1020000002035

申请日：2000-01-17

Applicant: 삼성전자주식회사

Inventor： 신유철

IPC: H01L21/8242

Abstract: PURPOSE: A method for manufacturing semiconductor devices is provided to reduce the height between a gate electrode and a bitline by forming a bitline immediately after a bitline contact plug simultaneously formed with a bitline contact pad is formed. CONSTITUTION: The method forms a gate pattern(106) in a semiconductor substrate(100) in which a device isolation film is formed to define an active region(104). A source/drain region(108) is formed in the active region exposed at both sides of the gate pattern by means of an ion implantation process. A gate spacer(110) is formed at both sides of the gate pattern. Source/drain electrodes(112a,112b) connected to the drain electrode(112b) are formed on the drain electrode. A storage electrode connected to the source electrode is formed on the source electrode.

Abstract translation: 目的：提供一种制造半导体器件的方法，用于通过在与位线接触焊盘同时形成的位线接触插塞之后立即形成位线来减小栅电极和位线之间的高度。 构成：该方法在其中形成器件隔离膜以形成有源区（104）的半导体衬底（100）中形成栅极图案（106）。 通过离子注入工艺在栅极图案的两侧露出的有源区中形成源/漏区（108）。 栅极间隔物（110）形成在栅极图案的两侧。 在漏电极上形成连接到漏电极（112b）的源/漏电极（112a，112b）。 在源电极上形成连接到源电极的存储电极。

公开(公告)号：KR1020000074841A

公开(公告)日：2000-12-15

申请号：KR1019990019061

申请日：1999-05-26

Applicant: 삼성전자주식회사

Inventor： 신유철 ,  신광식 ,  허성회 ,  오흥권

IPC: H01L21/76

Abstract: PURPOSE: A method for manufacturing a trench isolation is provided to make a projected range of source/drain impurity ions have a relatively small region on an interface between an active region and a non active region, by forming a trench isolation layer higher than a substrate, and by forming a spacer on a sidewall of the isolation layer. CONSTITUTION: A trench etch mask is formed by sequentially forming the first insulating layer and the second insulating layer on a substrate(210). A trench is formed on the substrate by using the trench etch mask. The trench is filled up with the third insulating layer. The second insulating layer is eliminated to form a trench isolation layer(218) higher than the substrate. A gate electrode layer(224) is formed in an active region(A) of the substrate. A low density source/drain(226) is formed by injecting low density impurity ions into the active region of the substrate. Spacers(228a,228b) are formed on sidewalls of the trench isolation layer and gate electrode layer. A high density source/drain is formed by injecting high density impurity ions into the active region of the substrate.

Abstract translation: 目的：提供一种用于制造沟槽隔离的方法，通过形成比衬底高的沟槽隔离层，使源/漏杂质离子的投影范围在有源区和非有源区之间的界面上具有相对小的区域 并且通过在隔离层的侧壁上形成间隔物。 构成：通过在衬底（210）上依次形成第一绝缘层和第二绝缘层来形成沟槽蚀刻掩模。 通过使用沟槽蚀刻掩模在衬底上形成沟槽。 沟槽填充有第三绝缘层。 消除第二绝缘层以形成比衬底高的沟槽隔离层（218）。 栅极电极层（224）形成在衬底的有源区（A）中。 通过将低密度杂质离子注入到衬底的有源区中形成低密度源极/漏极（226）。 间隔物（228a，228b）形成在沟槽隔离层和栅极电极层的侧壁上。 通过将高密度杂质离子注入到衬底的有源区中形成高密度源极/漏极。

公开(公告)号：KR1019990080898A

公开(公告)日：1999-11-15

申请号：KR1019980014473

申请日：1998-04-23

Applicant: 삼성전자주식회사

Inventor： 신유철

IPC: H01L21/8242

Abstract: 본 발명은 사진 공정에서의 마진을 확보하고, 선택비를 개선하는 반도체 메모리 장치의 제조 방법 및 그의 레이아웃에 관한 것으로, 게이트 전극층의 상부 표면이 노출될 때까지 도전층을 CMP 공정으로 도전층 패드가 형성된다. 도전층 패드를 포함하여 반도체 기판 상에 스토리지 노드 콘택홀 형성 영역과 비트 라인 콘택홀 형성 영역을 포함하는 엑티브 영역을 정의하기 위한 마스크 패턴이 형성된다. 마스크 패턴을 사용하고, 게이트 전극층의 절연층 및 소자 격리막을 식각 정지층으로 사용하여 도전층 패드 및 그 하부의 반도체 기판의 일부 두께가 식각된다. 이와 같은 반도체 메모리 장치의 제조 방법 및 그의 레이아웃에 의해서, 폴리실리콘 패드 형성시 폴리실리콘과 질화막(또는 산화막)과의 선택비를 이용함으로써 높은 선택비를 얻을 수 있고, 반도체 기판에 소자 격리막을 한 번에 형성하지 않고 나누어 형성함으로써 사진 공정에서 마진을 확보할 수 있다.