公开(公告)号：KR100383636B1

公开(公告)日：2003-05-16

申请号：KR1020000029548

申请日：2000-05-31

Applicant: 삼성전자주식회사

Inventor： 이대엽

IPC: H01L21/027

CPC classification number: H01L21/31138 ,  G03F7/095 ,  G03F7/168 ,  H01L21/0273 ,  H01L21/31144

Abstract: A method of generating a circuit pattern of a semiconductor device, comprises sequentially depositing a first patternable layer and photoresist layer, converting a given depth of the photoresist layer into a second patternable layer insoluble in an alkaline solution, selectively etching the second patternable layer to form a photoresist pattern mask, applying an O2 plasma through the photoresist pattern mask to form a photoresist pattern in the unconverted part of the photoresist layer, and selectively etching the first patternable layer by using the photoresist pattern as a mask to obtain a fine circuit pattern.

Abstract translation: 产生半导体器件的电路图案的方法包括顺序地沉积第一可图案化层和光致抗蚀剂层，将给定深度的光致抗蚀剂层转换成不溶于碱性溶液的第二可图案化层，选择性蚀刻第二可图案化层以形成 光致抗蚀剂图案掩模，通过光致抗蚀剂图案掩模施加O 2等离子体以在光致抗蚀剂层的未转换部分中形成光致抗蚀剂图案，并且通过使用光致抗蚀剂图案作为掩模选择性地蚀刻第一图案化层以获得精细电路图案。

公开(公告)号：KR1020030010323A

公开(公告)日：2003-02-05

申请号：KR1020010045223

申请日：2001-07-26

Applicant: 삼성전자주식회사

Inventor： 이재한 ,  이대엽

IPC: H01L21/8247

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11536 ,  H01L27/11543

Abstract: PURPOSE: A method for fabricating a flash memory device using a self-aligned non-exposure pattern formation process is provided to form a hard mask for defining a control gate pattern on a cell region without an exposure process by using a lower stepped portion formed with a floating gate and an inter-gate dielectric. CONSTITUTION: A conductive layer, a blocking layer, and a photoresist layer are formed on a substrate including a floating gate pattern and an inter-gate dielectric pattern(100). A photoresist pattern is formed by developing the photoresist layer(110). A blocking layer pattern is formed by removing the exposed blocking layer(120). The photoresist pattern is removed(130). A hard mask is formed by oxidizing a surface of the exposed conductive layer(140,150). The blocking layer pattern is removed(160). A control gate is formed by etching the conductive layer. A stack gate is formed by removing the hard mask(170).

Abstract translation: 目的：提供一种使用自对准非曝光图案形成工艺制造闪速存储器件的方法，以形成硬掩模，用于通过使用形成有下列阶形部分的曝光处理来限定单元区域上的控制栅极图案 浮栅和栅极间电介质。 构成：在包括浮置栅极图案和栅极间电介质图案（100）的衬底上形成导电层，阻挡层和光致抗蚀剂层。 通过显影光致抗蚀剂层（110）形成光致抗蚀剂图案。 通过去除暴露的阻挡层（120）形成阻挡层图案。 去除光致抗蚀剂图案（130）。 通过氧化暴露的导电层（140,150）的表面形成硬掩模。 去除阻挡层图案（160）。 通过蚀刻导电层形成控制栅极。 通过去除硬掩模（170）形成堆叠栅极。

公开(公告)号：KR1020020052643A

公开(公告)日：2002-07-04

申请号：KR1020000082054

申请日：2000-12-26

Applicant: 삼성전자주식회사

Inventor： 유지용 ,  이대엽 ,  이정우 ,  이석주 ,  이재한

IPC: H01L21/027

CPC classification number: H01L21/0274 ,  G03F7/0035 ,  H01L21/76802 ,  H01L21/76829

Abstract: PURPOSE: A formation method of a pattern by using lower step-coverage is provided to simplify manufacturing processes by forming a pattern without exposure and to prevent misalignment by reducing a minimal width of the pattern according to the reduction of a design rule. CONSTITUTION: A formation method of a pattern comprises a first step(120) forming an estimated layer to be patterned and a photoresist, a second step(125) baking the resultant structure, a third step(130) forming a photoresist pattern by performing a development using development solution, a fourth step(140) forming a defined pattern by removing the exposed portions of the estimated layer to be patterned using the photoresist pattern as a mask, the last step(150) removing the photoresist pattern. At this point, no exposure process is performed, so that the number of processes is reduced.

Abstract translation: 目的：提供通过使用较低阶梯覆盖的图案的形成方法，以通过形成不暴露的图案来简化制造工艺，并且通过根据设计规则的减少减小图案的最小宽度来防止错位。 构成：图案的形成方法包括形成要图案化的估计层和光致抗蚀剂的第一步骤（120），烘焙所得结构的第二步骤（125），通过执​​行形成光致抗蚀剂图案的第三步骤（130） 显影使用显影溶液，第四步骤（140）通过使用光致抗蚀剂图案作为掩模去除待图案化的估计层的曝光部分来形成限定图案，最后步骤（150）去除光致抗蚀剂图案。 此时，不进行曝光处理，从而减少处理次数。

公开(公告)号：KR1020000012967A

公开(公告)日：2000-03-06

申请号：KR1019980031568

申请日：1998-08-03

Applicant: 삼성전자주식회사

Inventor： 이재한 ,  여기성 ,  이대엽

IPC: H01L21/265

Abstract: PURPOSE: A semiconductor's manufacturing process is provided which forms an align key or an overlay key when an ion implant acts as a critical step like a logic circuit or is performed at the first step of the process. CONSTITUTION: In the manufacturing process, a buffer layer (102) is formed on the upper board of a semiconductor before the ion implant. Then, a mask layer (104) is formed on the upper board of the buffer layer (102). In the next step, if the mask layer is removed after the ion implant where a dopant (106) is implanted in a silicon substrate (100) and the buffer layer(102) the ion implanted area is divided from the un-implanted area on the buffer layer(102). In the following process, because of such a division the values of a refractive index and an absorption rate differ between two areas when a laser and a broad band are used as the align wavelength and a mask is aligned by the difference of the refractive index and the absorption rate.

Abstract translation: 目的：提供一种半导体制造工艺，当离子注入作为像逻辑电路的关键步骤或在该过程的第一步中执行时，形成对准键或覆盖键。 构成：在制造过程中，在离子注入之前在半导体的上板上形成缓冲层（102）。 然后，在缓冲层（102）的上板上形成掩模层（104）。 在下一步骤中，如果在离子注入之后去除掩模层，其中将掺杂剂（106）注入硅衬底（100）和缓冲层（102）中，则将离子注入区域与未注入的区域分开 缓冲层（102）。 在下面的过程中，由于这样的划分，当使用激光和宽带作为对准波长时，折射率和吸收率的值在两个区域之间是不同的，并且掩模通过折射率和 吸收率。

公开(公告)号：KR1019980066715A

公开(公告)日：1998-10-15

申请号：KR1019970002412

申请日：1997-01-28

Applicant: 삼성전자주식회사

Inventor： 이대엽

IPC: G03F7/039

Abstract: 본 발명은 화학식 1의 폴리머를 포함하는 화학증폭형 레지스트 조성물을 제공한다.
[화학식 1]

公开(公告)号：KR1019980010625A

公开(公告)日：1998-04-30

申请号：KR1019960029316

申请日：1996-07-19

Applicant: 삼성전자주식회사

Inventor： 이대엽 ,  정동원 ,  박춘근

IPC: G03F7/075 ,  G03F7/38

公开(公告)号：KR101966894B1

公开(公告)日：2019-08-13

申请号：KR1020120129045

申请日：2012-11-14

Applicant: 삼성전자주식회사

Inventor： 김철호 ,  강문종 ,  김봉철 ,  박초롱 ,  이대엽 ,  이상호 ,  이재한

IPC: H01L21/8247 ,  H01L27/115

公开(公告)号：KR1020140061879A

公开(公告)日：2014-05-22

申请号：KR1020120129045

申请日：2012-11-14

Applicant: 삼성전자주식회사

Inventor： 김철호 ,  강문종 ,  김봉철 ,  박초롱 ,  이대엽 ,  이상호 ,  이재한

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L21/28273 ,  H01L21/0273 ,  H01L21/67063 ,  H01L21/76897

Abstract: The present invention is a method of forming a step shape pattern. According to the method, an etching target layer is formed on a substrate. Photoresist patterns which have different photoresist properties are alternately stacked on the etching target layer. A photoresist structure which has an edge part of a step shape is formed. The etching target layer is etched by using the photoresist structure as an etching mask to form a step shape pattern. By doing so, the number of etching processes is reduced and thereby the step shape pattern can be formed by a simple process.

Abstract translation: 本发明是形成台阶形状图案的方法。 根据该方法，在基板上形成蚀刻对象层。 具有不同光致抗蚀剂性质的光刻胶图案交替堆叠在蚀刻目标层上。 形成具有台阶形状的边缘部分的光致抗蚀剂结构。 通过使用光致抗蚀剂结构作为蚀刻掩模蚀刻蚀刻目标层以形成台阶形状图案。 通过这样做，减少了蚀刻工艺的数量，从而可以通过简单的工艺形成台阶形状图案。

公开(公告)号：KR1020120134216A

公开(公告)日：2012-12-12

申请号：KR1020110052993

申请日：2011-06-01

Applicant: 삼성전자주식회사

Inventor： 김봉철 ,  이대엽

IPC: H01L21/28 ,  H01L21/027 ,  H01L21/8247 ,  H01L21/8242

CPC classification number: H01L21/76877 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76816 ,  H01L27/10894 ,  H01L27/11529 ,  H01L21/0274 ,  G03F1/80 ,  H01L21/28123

Abstract: PURPOSE: A forming method for a metal contact using DPT(double patterning technology) is provided to simplify a metal contact forming process of a semiconductor device by forming a metal contact in a peri region with a metal contact in a cell region together. CONSTITUTION: A first insulation layer and a first mask layer are successively formed on a target layer. A first opening which exposes the first insulation layer and a first mask pattern with a first hole which exposes the first insulation layer to a peri region are formed by etching the first mask layer. A line shaped first sacrificial layer pattern is formed on the first mask pattern of a cell region and the exposed first insulation layer using a DPT(double patterning technology) process. A contact hole exposing the target layer is formed by etching the first insulation layer. A metal contact(190) is formed by filling the contact hole with the metal material.

Abstract translation: 目的：提供使用DPT（双重图案形成技术）的金属接触的形成方法，以通过在细胞区域中与金属接触在周边区域形成金属接触来简化半导体器件的金属接触形成工艺。 构成：在目标层上依次形成第一绝缘层和第一掩模层。 通过蚀刻第一掩模层，形成将第一绝缘层露出的第一开口和具有将第一绝缘层暴露于周边区域的第一孔的第一掩模图案。 使用DPT（双重图案形成技术）工艺，在单元区域的第一掩模图案和暴露的第一绝缘层上形成线状的第一牺牲层图案。 暴露目标层的接触孔通过蚀刻第一绝缘层而形成。 通过用金属材料填充接触孔来形成金属接触件（190）。

公开(公告)号：KR1020100081832A

公开(公告)日：2010-07-15

申请号：KR1020090001245

申请日：2009-01-07

Applicant: 삼성전자주식회사

Inventor： 김봉철 ,  이대엽 ,  조상연 ,  구자민 ,  손병환

IPC: H01L21/027

CPC classification number: H01L21/3086 ,  H01L21/0337 ,  H01L21/32139 ,  H01L27/11521 ,  G03F7/0002 ,  G03F7/70475

Abstract: PURPOSE: A method for forming the pattern of a semiconductor device is provided to overcome misalignment problems between patterns by simultaneously forming patterns with various widths through one photolithography process. CONSTITUTION: A first mold mask pattern and a second mold mask pattern with different widths are formed on a substrate(300). A pair of first spacers(350A) are formed to cover both sidewalls of the first mold mask pattern. A pair of second spacers(350B) are formed to cover both sidewalls of the second mold mask pattern. The substrate is exposed through a first gap between the first spacer patterns and a second gap between the second spacer patterns. Mask patterns with wide widths(370A, 370B) are formed to cover the inside of the second gap and the second spacers. The substrate is etched using the first spacers, the second spacers, and the mask patterns with the wide widths.

Abstract translation: 目的：提供一种用于形成半导体器件的图案的方法，以通过一个光刻工艺同时形成具有各种宽度的图案来克服图案之间的未对准问题。 构成：在基板（300）上形成具有不同宽度的第一模具掩模图案和第二模具掩模图案。 形成一对第一间隔件（350A）以覆盖第一模具掩模图案的两个侧壁。 形成一对第二间隔件（350B）以覆盖第二模具掩模图案的两个侧壁。 衬底通过第一间隔图案之间的第一间隙和第二间隔图案之间的第二间隙而暴露。 形成宽宽度（370A，370B）的掩模图案以覆盖第二间隙和第二间隔物的内部。 使用第一间隔物，第二间隔物和具有宽宽度的掩模图案蚀刻衬底。