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公开(公告)号：KR1020070115482A
公开(公告)日：2007-12-06
申请号：KR1020060049993
申请日：2006-06-02
Applicant: 삼성전자주식회사
IPC: H01L29/786
CPC classification number: H01L29/78603 , H01L29/78645 , H01L29/78621
Abstract: A thin film transistor formed on a flexible substrate and a manufacturing method thereof are provided to form uniformly offset regions into each device respectively by forming the offset region between dual gates, even if a mis-alignment exists. A polysilicon layer(44) including a source and a drain regions is formed on a flexible substrate(40). A gate stack(S) is formed on a channel region of the polysilicon layer. The gate stack comprises a first gate stack(S1) and a second gate stack(S2), and an offset region is exposed between the first and the second gate stacks.
Abstract translation: 形成在柔性基板上的薄膜晶体管及其制造方法分别通过在双栅极之间形成偏移区域来分别形成均匀的偏移区域，即使存在错误对准。 在柔性基板（40）上形成包括源区和漏区的多晶硅层（44）。 在多晶硅层的沟道区上形成栅叠层（S）。 栅极堆叠包括第一栅极堆叠（S1）和第二栅极堆叠（S2），并且偏移区域暴露在第一和第二栅极堆叠之间。
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公开(公告)号：KR1020070074748A
公开(公告)日：2007-07-18
申请号：KR1020060002687
申请日：2006-01-10
Applicant: 삼성전자주식회사
IPC: H01L29/786 , H05B33/00
CPC classification number: H01L29/78645 , H01L27/1288 , H01L27/3244 , H01L29/78624 , H01L29/78696 , H01L27/1214
Abstract: A transistor is provided to reduce fabricating cost of a transistor and a display using the transistor by enabling formation of an offset structure without using a mask. Two polycrystalline silicon layers(10a) are disposed in parallel with each other, having doped high-conductive regions at their both ends and a channel region between the two high-conductive regions. A gate(12) is extended in a direction crossing the two polycrystalline silicon layers. A gate insulation layer is interposed between the gate and the polycrystalline silicon layers. Low-conductive regions(10e) are formed between the channel region of polycrystalline silicon and the high-conductive region, confronting each other and adjoining the edge of one side of the gate. Impurities having a low density can be doped into the low-conductive region as compared with the high-conductive region.
Abstract translation: 提供晶体管以通过在不使用掩模的情况下形成偏移结构来降低晶体管和使用晶体管的显示器的制造成本。 两个多晶硅层（10a）彼此平行地设置，在其两端具有掺杂的高导电区域和两个高导电区域之间的沟道区域。 栅极（12）沿与两个多晶硅层交叉的方向延伸。 栅极绝缘层介于栅极和多晶硅层之间。 低导电区域（10e）形成在多晶硅的沟道区域和相互面对并邻接栅极一侧边缘的高导电区域之间。 与高导电区域相比，可以将具有低密度的杂质掺杂到低导电区域中。
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公开(公告)号：KR1020050073855A
公开(公告)日：2005-07-18
申请号：KR1020040001962
申请日：2004-01-12
Applicant: 삼성전자주식회사
IPC: H05B33/22
CPC classification number: H01L51/0097 , H01L27/3244 , H01L51/5253 , H01L2251/5338 , Y02E10/549 , Y02P70/521
Abstract: 본 발명은 플렉셔블 디스플레이에 관한 것이다. 플라스틱 기판을 사용하는 플렉셔블 디스플레이에 있어서, 플라스틱 기판; 및 상기 플라스틱 기판 상에 형성된 보호층;을 포함시킴으로써, 플라스틱 기판을 보호하고, 폴리 실리콘층의 형성을 위한 열처리 공정을 충분히 행할 수 있으며, 보호층에 의한 레이져 광의 반사 또는 흡수를 통하여 보다 우수한 표면 및 성질을 지닌 폴리 실리콘층을 형성시킴으로써 결과적으로 플렉셔블 디스플레이의 성능 및 수명을 크게 향상시킬 수 있다.
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公开(公告)号：KR1020050024896A
公开(公告)日：2005-03-11
申请号：KR1020030062129
申请日：2003-09-05
Applicant: 삼성전자주식회사
IPC: H04L12/28
CPC classification number: H04W84/18 , G06Q30/0203
Abstract: PURPOSE: An information collecting system and method using a mobile ad hoc network are provided to obtain a result of ballot or questionnaire quickly and effectively. CONSTITUTION: An initial setting node(100) broadcasts question items to each node and controls to collect a response message to the question items in order to obtain certain information. A responding node(200) creates a response message with respect to the question items which have been broadcast by the initial setting node(100), and transmits the response message. A collecting node(300) collects the response message transmitted by the responding node(200) and calculates statistics with respect to collected messages.
Abstract translation: 目的：提供使用移动自组织网络的信息收集系统和方法，以快速有效地获得投票或调查问卷的结果。 构成：初始设置节点（100）向每个节点广播问题项，并控制收集对问题项目的响应消息，以获得某些信息。 响应节点（200）创建关于由初始设置节点（100）广播的问题项目的响应消息，并发送响应消息。 收集节点（300）收集由响应节点（200）发送的响应消息，并且针对收集的消息计算统计信息。
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公开(公告)号：KR102243553B1
公开(公告)日：2021-04-22
申请号：KR1020140089914
申请日：2014-07-16
Applicant: 삼성전자주식회사
IPC: C09K11/06 , H01L51/50 , H01L27/146
Abstract: 제1 전극, 상기제1 전극의일면에위치하고제1 p형반도체와제1 n형반도체가이종접합을형성하는흡광층, 상기흡광층의일면에위치하고상기흡광층보다작은반치폭을가지는제2 p형반도체또는제2 n형반도체를포함하는흡광보조층, 상기흡광보조층의일면에위치하는전하보조층, 그리고상기전하보조층의일면에위치하는제2 전극을포함하는유기광전소자및 이미지센서에관한것이다.
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Patent Agency Ranking
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公开(公告)号：KR101920848B1
公开(公告)日：2018-11-22
申请号：KR1020120101781
申请日：2012-09-13
Applicant: 삼성전자주식회사
IPC: H01L51/50 , H01L51/42 , H01L27/146
CPC classification number: H01L51/442 , H01L27/307 , H01L51/5234 , Y02E10/549
Abstract: 제1 전극, 상기제1 전극의일면에서상기제1 전극과접촉되어있는금속나노층, 상기금속나노층의일면에위치하는활성층, 그리고상기활성층의일면에위치하는제2 전극을포함하는유기광전소자및 이를포함하는이미지센서에관한것이다.
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公开(公告)号：KR101713994B1
公开(公告)日：2017-03-09
申请号：KR1020100138042
申请日：2010-12-29
Applicant: 삼성전자주식회사
IPC: H01L29/78
CPC classification number: H01L29/7869 , H01L29/78693
Abstract: 트랜지스터와그 제조방법및 트랜지스터를포함하는전자소자에관해개시되어있다. 개시된트랜지스터는채널층의백 채널영역(back channel region)에불소함유영역을구비할수 있다. 상기불소함유영역은불소를포함하는플라즈마로처리된영역일수 있다. 상기트랜지스터의소오스/드레인과채널층사이의계면영역은불소미함유영역일수 있다. 상기채널층은산화물반도체층일수 있다.
Abstract translation: 晶体管包括设置在栅极上方并包括氧化物半导体的沟道层。 源电极接触沟道层的第一端部，漏电极与沟道层的第二端部接触。 沟道层还包括形成在源极和漏极之间的沟道层的上部的含氟区。
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