公开(公告)号：KR1020100006059A

公开(公告)日：2010-01-18

申请号：KR1020080066222

申请日：2008-07-08

Applicant: 삼성전자주식회사

Inventor： 성정헌 ,  조중래 ,  김덕기 ,  황수정

IPC: H01L21/82

CPC classification number: H01L23/5252 ,  G11C17/18 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PURPOSE: An electric fuse device and an operation method thereof are provided to improve programming pre/post resistance ratio and have simple structure and small size. CONSTITUTION: An electric fuse device comprises a fuse(100) and a drive component(200). The drive component is connected to the fuse and comprises a resistance change layer whose resistance is changed according to applied voltage. The resistance change layer has a metal-insulator transition property. The drive component comprises two electrodes and the resistance change layer between the two electrodes.

Abstract translation: 目的：提供一种电熔丝装置及其操作方法，以提高编程前/后电阻比，结构简单，体积小。 构成：电熔丝装置包括保险丝（100）和驱动部件（200）。 驱动部件连接到保险丝，并且包括其电阻根据施加的电压而改变的电阻变化层。 电阻变化层具有金属 - 绝缘体转移特性。 驱动部件包括两个电极和两个电极之间的电阻变化层。

公开(公告)号：KR1020090121012A

公开(公告)日：2009-11-25

申请号：KR1020080047094

申请日：2008-05-21

Applicant: 삼성전자주식회사

Inventor： 성정헌 ,  김덕기 ,  황수정

IPC: G11C29/04 ,  G11C5/14

CPC classification number: G11C29/787 ,  G11C17/16 ,  G11C17/18 ,  G11C29/808 ,  G11C2229/763

Abstract: PURPOSE: An electrical fuse device is provided to be used after completing the assembly of a package of a semiconductor chip. CONSTITUTION: An electrical fuse device includes plural fuses(10), a power source and a voltage controller. The power source applies programming voltage to the fuses, and the voltage controller is connected to the power source. The plural fuses are connected to the voltage controller in parallel, and the voltage controller includes a diode(30) of which break-down voltage is 1-5V. The voltage controller is prepared between the power source and the plural fuses.

Abstract translation: 目的：提供一种电熔丝装置，用于在完成半导体芯片封装的组装之后使用。 构成：电熔丝装置包括多个保险丝（10），电源和电压控制器。 电源对保险丝施加编程电压，电压控制器连接到电源。 多个保险丝并联连接到电压控制器，并且电压控制器包括击穿电压为1-5V的二极管（30）。 在电源和多个保险丝之间准备电压控制器。

公开(公告)号：KR1020090108457A

公开(公告)日：2009-10-15

申请号：KR1020080033880

申请日：2008-04-11

Applicant: 삼성전자주식회사

Inventor： 김덕기 ,  성정헌 ,  최상무 ,  황수정

IPC: H01L23/62

CPC classification number: H01L23/5252 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PURPOSE: An anti-fuse is provided to exclude a separate programming transistor by including a transistor structure. CONSTITUTION: An anti-fuse includes a first conductor(100), a second conductor(200), a dielectric layer, and a diffusion layer(120). The first conductor and the second conductor are separated. The dielectric layer is included between the first conductor and the second conductor. The diffusion layer is included between the dielectric layer and one among the first conductor and the second conductor. The dielectric layer includes one of Al oxide, Si oxide, and Si nitride. The diffusion layer includes Cr.

Abstract translation: 目的：提供反熔丝以通过包括晶体管结构来排除单独的编程晶体管。 构成：反熔丝包括第一导体（100），第二导体（200），电介质层和扩散层（120）。 第一导体和第二导体分开。 介电层包括在第一导体和第二导体之间。 扩散层包括在介电层和第一导体和第二导体中之间。 电介质层包括Al氧化物，Si氧化物和Si氮化物中的一种。 扩散层包括Cr。

公开(公告)号：KR1020090017040A

公开(公告)日：2009-02-18

申请号：KR1020070081459

申请日：2007-08-13

Applicant: 삼성전자주식회사

Inventor： 설광수 ,  박상진 ,  최상무 ,  이효석 ,  성정헌

IPC: H01L21/8247 ,  H01L27/115 ,  B82Y10/00

CPC classification number: H01L29/4234 ,  H01L21/28282 ,  H01L29/513 ,  H01L29/66833 ,  B82Y10/00

Abstract: A charge trap type nonvolatile memory device and a manufacturing method thereof are provided to prevent leakage of charge trapped in a charge storing layer through a blocking insulation film by using an aluminum oxide film as an insulation film. A charge trap type nonvolatile memory device comprises a tunneling film(16), a charge storing layer(18), a blocking insulation film(20), and a gate electrode(22). The blocking insulation film is formed by using an aluminum oxide film having larger energy band gap than an aluminum oxide film of gamma phase. The charge storing layer includes one among silicone nitride film, metal nano dot, and silicone nano dot, and is double layer structure or mixing structure.

Abstract translation: 提供了一种电荷阱型非易失性存储器件及其制造方法，以通过使用氧化铝膜作为绝缘膜来防止通过隔离绝缘膜捕获在电荷存储层中的电荷的泄漏。 电荷阱型非易失性存储器件包括隧穿膜（16），电荷存储层（18），阻挡绝缘膜（20）和栅电极（22）。 通过使用具有比γ相的氧化铝膜更大的能带隙的氧化铝膜来形成阻挡绝缘膜。 电荷存储层包括氮化硅膜，金属纳米点和有机硅纳米点之一，是双层结构或混合结构。

公开(公告)号：KR1020080082844A

公开(公告)日：2008-09-12

申请号：KR1020070023675

申请日：2007-03-09

Applicant: 삼성전자주식회사

Inventor： 최상무 ,  설광수 ,  박상진 ,  성정헌

IPC: H01L27/115 ,  H01L21/8247 ,  B82Y10/00

CPC classification number: H01L29/513 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/792 ,  H01L29/66833

Abstract: A charge trap type memory device is provided to minimize an interface reaction with a charge trap layer even through the charge trap layer is formed with a material including silicon by forming a blocking dielectric with a material including Gd or lanthanide. A tunnel dielectric(21) is formed on a substrate(11). First and second impurity regions(13,15) at which conductive impurities are doped are formed on the substrate. A charge trap layer(23) is formed on the tunnel dielectric. A blocking dielectric(25) is formed on the charge trap layer. The blocking dielectric is made of a material including Gd or lanthanide, aluminum, and nitrogen. The blocking dielectric is GdAlON. The charge trap layer is made of a material including silicon. The charge trap layer includes SiN material. The charge trap layer includes one of polysilicon, nitride, nano dots, and high-k dielectric. A gate electrode(27) is formed on the blocking dielectric.

Abstract translation: 提供电荷陷阱型存储器件，以尽可能减少与电荷陷阱层的界面反应，即使通过用包括Gd或镧系元素的材料形成阻挡电介质，通过包含硅的材料形成电荷陷阱层。 隧道电介质（21）形成在衬底（11）上。 在衬底上形成掺杂有导电杂质的第一和第二杂质区域（13,15）。 在隧道电介质上形成电荷陷阱层（23）。 阻挡电介质（25）形成在电荷陷阱层上。 阻挡电介质由包括Gd或镧系元素，铝和氮的材料制成。 阻挡电介质是GdAlON。 电荷陷阱层由包括硅的材料制成。 电荷陷阱层包括SiN材料。 电荷陷阱层包括多晶硅，氮化物，纳米点和高k电介质之一。 栅电极（27）形成在阻挡电介质上。