公开(公告)号：KR100396137B1

公开(公告)日：2003-08-27

申请号：KR1020010033065

申请日：2001-06-13

Applicant: 재단법인서울대학교산학협력재단

Inventor： 박병국 ,  이종덕 ,  정경훈 ,  성석강

IPC: H01L21/027

Abstract: PURPOSE: A method for forming ultra-fine multi-patterns is provided to obtain the ultra-fine multi-patterns of a desired size in a narrow interval by performing a multiple patterning process using a sidewall. CONSTITUTION: A pattern layer, the second pattern layer, and the first pattern layer are sequentially deposited on a substrate. The first pattern is formed on the first pattern layer. The first sidewall layer is deposited on the first pattern. A sidewall is formed by performing a dry etch process. The second pattern is formed by etching the second pattern layer. The sidewall is removed from the second pattern. The second sidewall layer is deposited on the second pattern. The second sidewall(22') is formed by performing the dry etch process. A pattern(P) is formed by etching the pattern layer.

Abstract translation: 目的：提供一种形成超精细多图案的方法，以通过使用侧壁执行多重图案化工艺来以窄间隔获得期望尺寸的超精细多图案。 构成：图案层，第二图案层和第一图案层依次沉积在基底上。 第一图案形成在第一图案层上。 第一侧壁层沉积在第一图案上。 通过执行干蚀刻工艺形成侧壁。 第二图案通过蚀刻第二图案层而形成。 侧壁从第二图案移除。 第二侧壁层沉积在第二图案上。 第二侧壁（22'）通过执行干式蚀刻工艺而形成。 通过蚀刻图案层形成图案（P）。

公开(公告)号：KR1020020068801A

公开(公告)日：2002-08-28

申请号：KR1020010009078

申请日：2001-02-22

Applicant: 재단법인서울대학교산학협력재단

Inventor： 박병국 ,  이종덕 ,  최영진

IPC: H01L29/78

Abstract: PURPOSE: A field effect transistor and a method for fabricating the same are provided to use a shallow electronic layer excited by a field effect as a source/drain region. CONSTITUTION: A gate insulating layer(2) is formed on a semiconductor substrate(1) by growing an oxide layer. A side gate material layer is formed by depositing and doping a polysilicon on the gate insulating layer(2). The side gate material layer is patterned. A source/drain diffusion layer(4) is formed by implanting ions into the semiconductor substrate(1). A silicon nitride layer(5) is deposited on the patterned side gate material layer. A silicon oxide layer is formed on the side gate material layer and the silicon nitride layer(5). A silicon oxide layer sidewall(6) is formed by etching the silicon oxide layer. A couple of side gate(3) is formed by etching a side gate material layer. A main gate(7) is formed by depositing and doping the polysilicon.

Abstract translation: 目的：提供场效应晶体管及其制造方法，以使用由场效应激发的浅电子层作为源/漏区。 构成：通过生长氧化物层，在半导体衬底（1）上形成栅绝缘层（2）。 通过在栅极绝缘层（2）上沉积和掺杂多晶硅来形成侧栅极材料层。 侧栅材料层被图案化。 源极/漏极扩散层（4）通过将离子注入到半导体衬底（1）中而形成。 在图案化的侧栅极材料层上沉积氮化硅层（5）。 在侧栅材料层和氮化硅层（5）上形成氧化硅层。 通过蚀刻氧化硅层形成氧化硅层侧壁（6）。 通过蚀刻侧栅材料层形成一对侧栅（3）。 通过沉积和掺杂多晶硅形成主栅极（7）。