公开(公告)号：KR100594967B1

公开(公告)日：2006-06-30

申请号：KR1020040098425

申请日：2004-11-29

Applicant: 한국과학기술원

Inventor： 김동현 ,  유회준

IPC: G06F15/173

Abstract: 본 발명은 크로스바 스위치에 관한 것으로서, 크로스바 스위치의 입/출력 포트가 공유할 수 있는 버스 형태의 공유 전송선을 추가하고 입/출력 포트의 대역폭 사용량에 따라 동적으로 추가된 공유 전송선을 할당함으로써 작은 면적 증가를 통해 유효 대역폭을 향상시킬 수 있는 이점이 있다.
크로스바, 스위치, 공유, 버퍼풀, 대역폭, 면적

公开(公告)号：KR1020060068397A

公开(公告)日：2006-06-21

申请号：KR1020040107070

申请日：2004-12-16

Applicant: 한국과학기술원

Inventor： 김선영 ,  유회준

IPC: H03M3/02

CPC classification number: H03M3/352 ,  H03M3/32 ,  H03M3/396 ,  H03M2201/6107

Abstract: 본 발명은 적응형 시그마 델타 변조기에 관한 것으로서, 입력신호의 크기를 감지하고 이를 변수화하여 변조기의 시스템 클럭 주파수와 적분기의 차수를 동적으로 제어함으로써 다양한 신호 대 잡음비(SNR)를 제공함으로써 임의의 입력에 대한 과도한 변조기의 성능을 완화시켜 입력신호에 적응하여 최적화된 성능을 제공하며 동시에 전력소모를 줄일 수 있는 이점이 있다.
적응형, 시그마 델타, 가변차수, 가변클럭, 신호대 잡음비, SNR, 소모전력

公开(公告)号：KR100463642B1

公开(公告)日：2004-12-29

申请号：KR1020030014021

申请日：2003-03-06

Applicant: 한국과학기술원

Inventor： 손주호 ,  우람찬 ,  유회준

IPC: G06F17/00

Abstract: PURPOSE: A multimedia process accelerating system is provided to embed an automatic code processing function in an assistant processor, and to process a single instruction of a main processor via a memory manager so that it extends an instruction system for a multimedia process. CONSTITUTION: The system comprises a coprocessor interface unit(101), a state control unit(104), a program control unit(202), an internal program memory(201), a pipeline follower(102), a decoder(103), a stream control unit(203), a multi mode SIMD(Single Instruction Multiple Data) register file(301), an adjuster(302), an SIMD data path(105), a precision degree control unit(303), and a memory manager(205). The coprocessor interface unit(101) connects a main processor to an assistant processor. The state control unit(104) controls an overall operations of the assistant processor, and stores a current state. The program control unit(202) and the internal program memory(201) store a program for executing the assistant processor and control an execution of the assistant processor. The pipeline follower(102) synchronizes an instruction pipeline of the main processor with that of the assistant processor. The decoder(103) decodes the instruction of the main processor, and generates a control signal on an overall data path of the assistant processor. The stream control unit(203) controls a process on an multimedia data stream in a memory area. The multi mode SIMD register file(301) makes it possible setting each data value for each mode. The adjuster(302) adjusts a vector register value read from the multi mode SIMD register file(301). The SIMD data path(105) processes plural data with a single instruction. The precision degree control unit(303) adjusts a dynamic range of a calculation result. The memory manager(205) controls both the main memory and the assistant memory to access the same memory.

Abstract translation: 目的：提供一种多媒体处理加速系统，用于将自动代码处理功能嵌入辅助处理器中，并通过存储器管理器处理主处理器的单个指令，从而扩展多媒体处理的指令系统。 该系统包括协处理器接口单元（101），状态控制单元（104），程序控制单元（202），内部程序存储器（201），流水线跟随器（102），解码器（103） 流控制单元（203），多模式SIMD（单指令多数据）寄存器文件（301），调整器（302），SIMD数据路径（105），精度控制单元（303）和存储器 经理（205）。 协处理器接口单元（101）将主处理器连接到辅助处理器。 状态控制单元（104）控制辅助处理器的整体操作，并存储当前状态。 程序控制单元（202）和内部程序存储器（201）存储用于执行辅助处理器的程序并控制辅助处理器的执行。 流水线跟随器（102）使主处理器的指令流水线与辅助处理器的指令流水线同步。 解码器（103）解码主处理器的指令，并且在辅助处理器的整个数据路径上产生控制信号。 流控制单元（203）控制存储区中的多媒体数据流的处理。 多模式SIMD寄存器文件（301）可以为每种模式设置每个数据值。 调整器（302）调整从多模式SIMD寄存器文件（301）读取的向量寄存器值。 SIMD数据路径（105）用单个指令处理多个数据。 精度控制单元（303）调整计算结果的动态范围。 存储器管理器（205）控制主存储器和辅助存储器访问相同的存储器。

公开(公告)号：KR1020040106603A

公开(公告)日：2004-12-18

申请号：KR1020030037038

申请日：2003-06-10

Applicant: 한국과학기술원

Inventor： 우람찬 ,  유회준

IPC: G06F7/52

CPC classification number: G06T15/005 ,  G06T15/04 ,  G06T2200/28

Abstract: PURPOSE: A dividing unit of a three dimensional computer graphic system is provided to eliminate MSBs(Most Significant Bits) of a dividend as many as leading zeros of a divisor when a perspective division operation needed in a texture mapping is performed. CONSTITUTION: The unit comprises a leading zero detector(110), a UV formatter(120), and a divider(130). The leading zero detector(110) receives a value of a divisor, which is a texture address value, and counts the number of the divisor. The UV formatter(120) receives values of dividends, which are also texture address values, eliminates MSBs of the dividends as many as counted zeros of the divisor or pads zeros under LSBs(Least Significant Bits) as many as the number of the eliminated ciphers. The divider(130) divides the newly formatted dividends with the divisor.

Abstract translation: 目的：提供一种三维计算机图形系统的分割单元，用于在执行纹理映射所需的透视分割操作时，消除与除数的前导零一样多的除数的MSB（最高有效位）。 构成：该单元包括前导零检测器（110），UV格式化器（120）和分隔器（130）。 前导零检测器（110）接收作为纹理地址值的除数值，并对除数的数进行计数。 UV格式化器（120）接收分红值，它们也是纹理地址值，消除除数除数除数以上的除数的MSB，或低于LSB（最低有效位）下的零点数除去密码数 。 分割器（130）将新格式化的股息与除数分开。

公开(公告)号：KR1020040067302A

公开(公告)日：2004-07-30

申请号：KR1020030004338

申请日：2003-01-22

Applicant: 한국과학기술원

Inventor： 최성대 ,  유회준

IPC: G11C15/00

Abstract: PURPOSE: A content addressable memory device for storing ternary information is provided to reduce the power consumption by using only one content addressable memory cell to store and compare the ternary information of 0, 1, and a don't care value. CONSTITUTION: A content addressable memory device for storing ternary information includes a positive and a negative bit line, an SRAM cell, a comparator, a positive and a negative don't care line, an index cell, a match line, and a match line controller. The positive and the negative lines are used as input/output lines of the SRAM cell(10). The comparator(20) is used for comparing the data of the positive and the negative lines with the stored data of the SRAM cell. The positive and the negative don't care lines are used as data input/output lines of the index cell(40) in order to indicate a data state of the content addressable memory device. The match line is used for outputting a compared result of the comparator. The match line controller(30) is used for outputting a matching result to the match line.

Abstract translation: 目的：提供一种用于存储三元信息的内容可寻址存储器件，以通过仅使用一个内容可寻址存储器单元来存储和比较0,1的三进制信息和不关心值来降低功耗。 构成：用于存储三元信息的内容可寻址存储器件包括正和负位线，SRAM单元，比较器，正负负极线，索引单元，匹配线和匹配线 控制器。 正极和负极线用作SRAM单元（10）的输入/输出线。 比较器（20）用于将正和负线的数据与SRAM单元的存储数据进行比较。 为了指示内容可寻址存储器件的数据状态，正线和负极不用线作为索引单元（40）的数据输入/输出线。 匹配线用于输出比较器的比较结果。 匹配线控制器（30）用于将匹配结果输出到匹配线。

公开(公告)号：KR100427523B1

公开(公告)日：2004-04-28

申请号：KR1020020007868

申请日：2002-02-14

Applicant: 한국과학기술원

Inventor： 우람찬 ,  유회준

IPC: G06T1/60 ,  G06T17/00

Abstract: PURPOSE: A texture memory access device of a three-dimensional computer graphic system is provided to improve texture mapping performance to produce more vivid three-dimensional computer graphics. CONSTITUTION: A texture memory access device of a three-dimensional computer graphic system includes a texture address aligner(210), a texture address comparator(220), a texture memory controller(230), a texture data register(240), and a texture data aligner(250). The texture address aligner receives a plurality of texture memory addresses from texture units(110) and aligns identical texture addresses. The texture address comparator compares the aligned addresses with addresses stored at the previous clock cycle to align identical texture addresses. The texture memory controller controls a texture memory using texture addresses output from the comparator. The texture data register temporarily stores data read from the texture memory. The texture data aligner realigns texture data according to control signals output from the texture address aligner and the texture address comparator to send the texture data to the texture units.

Abstract translation: 目的：提供三维计算机图形系统的纹理存储器访问装置，以提高纹理映射性能，产生更生动的三维计算机图形。 3，一种三维计算机图形系统的纹理存储器访问装置，包括纹理地址对齐器（210），纹理地址比较器（220），纹理存储器控制器（230），纹理数据寄存器（240）和 纹理数据对准器（250）。 纹理地址对准器从纹理单元（110）接收多个纹理存储器地址并且对齐相同的纹理地址。 纹理地址比较器将对齐的地址与前一个时钟周期中存储的地址进行比较，以对齐相同的纹理地址。 纹理存储器控制器使用从比较器输出的纹理地址来控制纹理存储器。 纹理数据寄存器临时存储从纹理存储器读取的数据。 纹理数据对准器根据从纹理地址对准器和纹理地址比较器输出的控制信号重新对准纹理数据，以将纹理数据发送到纹理单元。

公开(公告)号：KR1020030020141A

公开(公告)日：2003-03-08

申请号：KR1020010053827

申请日：2001-09-03

Applicant: 한국과학기술원

Inventor： 우람찬 ,  윤치원 ,  국정훈 ,  이세중 ,  유회준

IPC: G06F3/14

Abstract: PURPOSE: A three dimensional computer graphics operation system is provided to install a bandwidth equalizer between a main operation processor and three dimensional computer graphics accelerators having different bandwidths for a high efficient data transmission so that it can implement a real time three dimensional computer graphics at a portable terminal. CONSTITUTION: The system comprises three dimensional computer graphics accelerators(300), a moving picture regeneration accelerator(410), and a bandwidth equalizer (200). The moving picture regeneration accelerator(410), connected to a main operation processor(100) via the bandwidth equalizer(200), accelerates a display of the three dimensional computer graphics. The three dimensional computer graphics accelerators(300) are workstation level hardwares for accelerating three dimensional graphic display with a high speed. The bandwidth equalizer(200) is a bus structure for connecting the three dimensional computer graphic accelerator(300) and the moving picture regeneration accelerator(410) to the main operation processor(100). The bandwidth equalizer(200) synchronizes the bandwidth of the three dimensional computer graphics accelerator(300) to that of the main operation processor(100) for enabling a data transmission between them. Also, the bandwidth equalizer(200) synchronizes the bandwidth of the moving picture regeneration accelerator(410) with that of the main operation processor(100).

Abstract translation: 目的：提供一种三维计算机图形操作系统，用于在具有不同带宽的主操作处理器和三维计算机图形加速器之间安装带宽均衡器，用于高效数据传输，从而可以实现三维计算机图形处理 便携式终端。 构成：该系统包括三维计算机图形加速器（300），运动图像再生加速器（410）和带宽均衡器（200）。 经由带宽均衡器（200）连接到主操作处理器（100）的运动画面再生加速器（410）加速三维计算机图形的显示。 三维计算机图形加速器（300）是用于加速高速三维图形显示的工作站级硬件。 带宽均衡器（200）是用于将三维计算机图形加速器（300）和运动图像再生加速器（410）连接到主操作处理器（100）的总线结构。 带宽均衡器（200）使三维计算机图形加速器（300）的带宽与主操作处理器（100）的带宽同步，以实现它们之间的数据传输。 此外，带宽均衡器（200）使运动图像再生加速器（410）的带宽与主运算处理器（100）的带宽同步。

公开(公告)号：KR100360550B1

公开(公告)日：2002-11-13

申请号：KR1020000079561

申请日：2000-12-21

Applicant: 한국과학기술원

Inventor： 박용하 ,  유회준

IPC: H03K19/0175

Abstract: 본 발명의 전류 피드백을 이용하는 저전력 버스 드라이버는 두 개의 논리신호를 입력받아 NAND 신호를 출력하는 NAND 게이트와; NAND 게이트의 입력신호 중의 하나를 포함하는 두 개의 입력신호를 입력받아 NOR 신호를 출력하는 NOR 게이트와; NAND 게이트의 출력신호를 입력받고, 드레인과 게이트가 전기적으로 연결되는 피드백 루프 PMOS와; NOR 게이트의 출력신호를 입력받고, 드레인과 게이트가 전기적으로 연결되며, 소스는 피드백 루프 PMOS의 소스와 전기적으로 연결되는 피드백 루프 NMOS와; 게이트는 피드백 루프 PMOS의 드레인과 전기적으로 연결되고, 소스에는 V
CC 가 입력되는 드라이버 PMOS와; 게이트는 피드백 루프 NMOS의 드레인과 전기적으로 연결되고, 드레인은 드라이버 PMOS의 드레인과 전기적으로 연결되며, 소스는 접지되는 드라이버 NMOS와; 드라이버 NMOS의 드레인과 드라이버 PMOS 드레인과 피드백 루프 NMOS의 소스와 피드백 루프 PMOS의 소스와 동시에 연결되며, 버스의 입력단에도 연결되는 출력라인을 구비한다. 본 발명에 의하면, 최소한의 면적으로 전체적인 성능의 변화가 없이 전력 소모가 적은 버스 드라이브의 집적이 가능하다.

公开(公告)号：KR1020020063385A

公开(公告)日：2002-08-03

申请号：KR1020010004015

申请日：2001-01-29

Applicant: 한국과학기술원

Inventor： 유회준 ,  윤치원

IPC: G06T1/60

CPC classification number: H04N19/423 ,  H04N19/61

Abstract: PURPOSE: A method for storing MPEG(Moving Picture Experts Group) compression image in a memory to reduce power consumption and a frame buffer structure therein are provided to integrate a frame buffer with logic, and to store data in a distributed 9-tile mapping type, so as to appropriately cope with application areas for processing MPEG image signals with low power consumption. And the frame buffer structure is provided to have 8 banks in a sub word line system capable of partial activation. CONSTITUTION: An optional image frame is divided into 8 by 8 pixel areas. The each divided block area is reestablished to mutually adjacent 9 block areas in a 3 by 3 type. The 8 by 8 pixel areas each consisting of the 9 mutually adjacent block areas reestablished in the 3 by 3 type are mapped to one row. The 8 by 8 pixel areas mapped to one row are distributed and stored in mutually different banks. Each of 64 pixels configuring the 8 by 8 pixel areas is represented with information of 8 bits, and one row stores information of 512 bits in total.

Abstract translation: 目的：提供一种用于将MPEG（运动图像专家组）压缩图像存储在存储器中以降低功耗的方法和其中的帧缓冲器结构，以将帧缓冲器与逻辑集成，并将数据存储在分布的9瓦映射类型 ，以便适当地处理用于处理低功耗的MPEG图像信号的应用领域。 并且提供帧缓冲器结构以在能够部分激活的子字线系统中具有8个存储体。 构成：可选的图像帧分为8×8像素区域。 每个划分的块区域以3×3类型重新建立到相邻的9个块区域。 由3×3类型重新建立的9个相互相邻的块区域构成的8×8像素区域被映射到一行。 映射到一行的8×8像素区域被分布并存储在相互不同的存储体中。 构成8×8像素区域的64像素中的每一个由8位的信息表示，一行总共存储512位的信息。

公开(公告)号：KR1020000056531A

公开(公告)日：2000-09-15

申请号：KR1019990005928

申请日：1999-02-23

Applicant: 한국과학기술원

Inventor： 유회준 ,  한선호 ,  이주호

IPC: H03L7/00

Abstract: PURPOSE: A mixed mode delay locked loop with quick synchronizing time and small jitter is provided to enable users to apply the device to chips which require high speed data transmission or low electric power. CONSTITUTION: A mixed mode delay locked loop with quick synchronizing time and small jitter includes a Voltage Controlled Delay Line(VCDL) of an analog circuit unit and a Fixed Delay Line(FDL) of a digital circuit unit. An analog circuit unit also includes a Phase Frequency Detector(PFD), an Internal Clock Detector(ID), a Charge Pump(CP), a 1/2Vcc generator, a loop filter, a Voltage to Current Converter, and a Voltage Controlled Delay Line(VCDL). The FDL of digital circuit unit includes a Replica of a clock driver which is a Monitor Driver, a Time to Digital Converter, and a Digital to Time Converter.

Abstract translation: 目的：提供具有快速同步时间和小抖动的混合模式延迟锁定环，使用户能够将设备应用于需要高速数据传输或低功耗的芯片。 构成：具有快速同步时间和小抖动的混合模式延迟锁定环路包括模拟电路单元的电压控制延迟线（VCDL）和数字电路单元的固定延迟线（FDL）。 模拟电路单元还包括相位检波器（PFD），内部时钟检测器（ID），电荷泵（CP），1 / 2Vcc发生器，环路滤波器，电压 - 电流转换器和电压控制延迟 线路（VCDL）。 数字电路单元的FDL包括时钟驱动器的复制品，时钟驱动器是监视器驱动器，时间到数字转换器和数字到时间转换器。