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公开(公告)号：KR1019930007049B1
公开(公告)日：1993-07-26
申请号：KR1019900021814
申请日：1990-12-26
Applicant: 한국전자통신연구원
IPC: G06F15/16
Abstract: The arbitrator processes independent data transmission processes of several handlers without mutual interruption to improve the efficiency of bus. It includes a control logic of address bus arbitration (1) for controlling arbitration, a multiplexer (2) for applying request signal (req) to one of the signal lines (ABRQ0-ABRQ12), a priority encoder (4) for detecting the signal of the highest priority, a 4 bit comparator (5) for comparing the output of the priority encoder (4) with its slot address signal (3), and an equity flag (6) for being checked to maintain the equity of address bus usage.
Abstract translation: 仲裁员处理多个处理程序的独立数据传输过程，而不会相互中断，从而提高总线的效率。 它包括用于控制仲裁的地址总线仲裁（1）的控制逻辑，用于向信号线（ABRQ0-ABRQ12）中的一条应用请求信号（req）的复用器（2），用于检测信号的优先级编码器 优先权编码器（4）的输出与其时隙地址信号（3）进行比较的4比特比较器（5）和被检查以维持地址总线使用权益的权利标志（6） 。
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公开(公告)号：KR1019930003993B1
公开(公告)日：1993-05-19
申请号：KR1019890019313
申请日：1989-12-22
Applicant: 한국전자통신연구원
IPC: G06F13/14
Abstract: The method transmits data smoothly through data bus by monopolizing the bus only in memory consulting operation of a processor and the related memory. It comprises the three stages: in the 1st stage a processor drives a certain address on address bus during a certain period of a bus clock; in the 2nd stage the memory selected by the certain address stores the certain address during the certain bus clock; and in the 3rd stage when the process of storing is completed, the processor cancells the occupation of the address bus the make other processor use the address bus.
Abstract translation: 该方法仅在处理器和相关存储器的存储器咨询操作中通过垄断总线通过数据总线平滑地传输数据。 它包括三个阶段：在第一阶段，一个处理器在总线时钟的一定时间段内在地址总线上驱动某个地址; 在第二阶段，特定地址选择的存储器在特定的总线时钟存储特定地址; 并且在存储过程完成的第三阶段中，处理器取消对其他处理器使用地址总线的占用地址总线。
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Patent Agency Ranking
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公开(公告)号：KR1019920009451B1
公开(公告)日：1992-10-16
申请号：KR1019900021856
申请日：1990-12-26
Applicant: 한국전자통신연구원
IPC: G06F13/38
Abstract: The circuit is for effectively controlling the storing function of a bus state analyzer to reduce the load of a system processor, the number of buffers and the complexity of the system. The circuit is composed of a condition meeting counter (2) for counting the condition meeting signal from an information detector (1) and generating the result, a controller (3) for generating enable signal corresponding to the output of the condition meeting counter (2), and an address generator (4) for generating address signal to store according to the enable signal from the controller (3) and sending it to an information storing section (5).
Abstract translation: 该电路用于有效地控制总线状态分析器的存储功能，以减少系统处理器的负载，缓冲器的数量和系统的复杂性。 电路由条件会议计数器（2）组成，用于从信息检测器（1）计数条件会议信号并产生结果;控制器（3），用于产生与条件会议计数器（2）的输出对应的使能信号 ）和地址发生器（4），用于根据来自控制器（3）的使能信号产生地址信号，并将其发送到信息存储部分（5）。
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