公开(公告)号：EP1535332B1

公开(公告)日：2012-04-11

申请号：EP03791994.1

申请日：2003-08-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： WIECZOREK, Karsten ,  BURBACH, Gert ,  FEUDEL, Thomas

IPC: H01L27/06 ,  H01L27/08 ,  H01L21/02

CPC classification number: H01L28/40 ,  H01L27/0629 ,  H01L27/0805

Abstract: A semiconductor device comprises a field effect transistor (250) and a passive capacitor (240), wherein the dielectric layer (221a) of the capacitor (240) is comprised of a high-k material, whereas the gate insulation layer (231) of the field effect transistor (250) is formed of an ultra thin oxide layer or oxynitride layer so as to provide for superior carrier mobility at the interface between the gate insulation layer and the underlying channel region. Since carrier mobility in the capacitor is not of great importance, the high-k material allows the provision of high capacitance per unit area while featuring a thickness sufficient to effectively reduce leakage current.

公开(公告)号：EP1668681A1

公开(公告)日：2006-06-14

申请号：EP04784756.1

申请日：2004-09-17

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： KAMMLER, Thorsten ,  WIECZOREK, Karsten ,  FRENKEL, Austin

IPC: H01L21/285

CPC classification number: H01L21/28518 ,  H01L21/28052 ,  H01L29/665

Abstract: By forming a buried nickel silicide layer (260A) followed by a cobalt silicide layer (261A) in silicon containing regions, such as a gate electrode of a field effect transistor, the superior characteristics of both silicides may be combined so as to provide the potential for further device scaling without unduly compromising the sheet resistance and the contact resistance of scaled silicon circuit features.

公开(公告)号：EP1479102A1

公开(公告)日：2004-11-24

申请号：EP02796111.9

申请日：2002-12-20

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： WIECZOREK, Karsten ,  HORSTMANN, Manfred ,  STEPHAN, Rolf

IPC: H01L21/285 ,  H01L21/8242

CPC classification number: H01L21/324 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/4933 ,  H01L29/665

Abstract: A method is disclosed in which different metal layers (240, 242) are sequentially deposited on silicon-containing regions so that the type and thickness of the metal layers (240, 242) may be adapted to specific characteristics of the underlying silicon-containing regions. Subsequently, a heat treatment is performed to convert the metals into metal silicides so as to improve the electrical conductivity of the silicon-containing regions. In this way, silicide portions (241, 243) may be formed that are individually adapted to specific silicon-containing regions so that device performance of individual semiconductor elements or the overall performance of a plurality of semiconductor elements may significantly be improved. Moreover, a semiconductor device is disclosed comprising at least two silicon-containing regions having formed therein differing silicide portions (241, 243), wherein at least one silicide portion comprises noble metal.

公开(公告)号：EP1479100A1

公开(公告)日：2004-11-24

申请号：EP02807094.4

申请日：2002-12-20

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： WIECZOREK, Karsten ,  HORSTMANN, Manfred ,  STEPHAN, Rolf

IPC: H01L21/28

CPC classification number: H01L21/823443 ,  H01L21/823418 ,  H01L29/665

Abstract: A method is disclosed in which differing metal layers are sequentially deposited on silicon-containing regions so that the type and thickness of the metal layers may be adapted to specific characteristics of the underlying silicon-containing regions. Subsequently, a heat treatment is performed to convert the metals into metal silicides so as to improve the electrical conductivity of the silicon-containing regions. In this way, silicide portions may be formed that are individually adapted to specific silicon-containing regions so that device performance of individual semiconductor elements or the overall performance of a plurality of semiconductor elements may be significantly improved. Moreover, a semiconductor device is disclosed comprising at least two silicon-containing regions having formed therein differing silicide portions, wherein at least one silicide portion comprises a noble metal.

公开(公告)号：EP1334522A1

公开(公告)日：2003-08-13

申请号：EP01977517.0

申请日：2001-10-04

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： HORSTMANN, Manfred ,  WIECZOREK, Karsten ,  HAUSE, Frederick, N.

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/768 ,  H01L29/49

CPC classification number: H01L29/4983 ,  H01L21/28247 ,  H01L23/5329 ,  H01L29/41775 ,  H01L29/6659 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A transistor device (200) is disclosed, having an insulating material disposed between the gate electrode (204) and the drain and source lines, wherein the dielectric constant of the insulating amterial is 3.5 or less. Accodingly, the capacitance between the gate electrode and the drain and source lines can be reduced, thereby improving signal performance of the field effect transistor (200) with decreased cross talk noise.

公开(公告)号：EP1479102B1

公开(公告)日：2010-08-11

申请号：EP02796111.9

申请日：2002-12-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： WIECZOREK, Karsten ,  HORSTMANN, Manfred ,  STEPHAN, Rolf

IPC: H01L21/285 ,  H01L21/8242

CPC classification number: H01L21/324 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/4933 ,  H01L29/665

Abstract: A method is disclosed in which different metal layers (240, 242) are sequentially deposited on silicon-containing regions so that the type and thickness of the metal layers (240, 242) may be adapted to specific characteristics of the underlying silicon-containing regions. Subsequently, a heat treatment is performed to convert the metals into metal silicides so as to improve the electrical conductivity of the silicon-containing regions. In this way, silicide portions (241, 243) may be formed that are individually adapted to specific silicon-containing regions so that device performance of individual semiconductor elements or the overall performance of a plurality of semiconductor elements may significantly be improved. Moreover, a semiconductor device is disclosed comprising at least two silicon-containing regions having formed therein differing silicide portions (241, 243), wherein at least one silicide portion comprises noble metal.

公开(公告)号：EP1245045B1

公开(公告)日：2007-12-26

申请号：EP00952341.6

申请日：2000-07-31

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： HORSTMANN, Manfred ,  WIECZOREK, Karsten ,  BURBACH, Gert

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5222 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  H01L2924/0002 ,  H01L2924/00

Abstract: There is provided a semiconductor device comprising an insulating layer (108) which is partly formed of porous material, and a method for fabricating the device. A stray capacitance of adjacent wiring lines is significantly reduced by reducing the amount of material, i.e., by using porous material in the insulating layer (108) of a metallization layer. In one embodiment, the porous layer (108) may be fabricated separately on a further substrate and is subsequently transferred to the product wafer while the further substrate and the product wafer are appropriately aligned to each other. In this way, fabrication of complete metallization layers having a reduced dielectric constant in advance or concurrently with the product wafer carrying the MOS structure is possible. Due to the reduced capacitance of the wiring lines of the metallization layer, signal performance and/or power consumption of an integrated circuit is improved.

公开(公告)号：EP1476899B1

公开(公告)日：2007-03-07

申请号：EP02787067.4

申请日：2002-12-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： WIECZOREK, Karsten ,  GRAETSCH, Falk ,  KRUEGEL, Stephan

IPC: H01L21/311 ,  H01L21/318 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/314

CPC classification number: H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823462 ,  H01L21/823857 ,  H01L29/513 ,  H01L29/518

Abstract: A method of forming oxide layers of different thickness on a substrate (1) is disclosed, wherein the oxide layers preferably serve as gate insulation layers of field effect transistors. The method allows to form very thin, high quality oxide layers with a reduced number of masking steps compared to the conventional processing, wherein the thickness difference can be maintained within a range of some tenths of a nanometer. The method substantially eliminates any high temperature oxidations and is also compatible with most chemical vapor deposition techniques used for gate dielectric deposition in sophisticated semiconductor devices

公开(公告)号：EP1535332A1

公开(公告)日：2005-06-01

申请号：EP03791994.1

申请日：2003-08-29

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： WIECZOREK, Karsten ,  BURBACH, Gert ,  FEUDEL, Thomas

IPC: H01L27/06 ,  H01L27/08 ,  H01L21/02

CPC classification number: H01L28/40 ,  H01L27/0629 ,  H01L27/0805

Abstract: A semiconductor device comprises a field effect transistor (250) and a passive capacitor (240), wherein the dielectric layer (221a) of the capacitor (240) is comprised of a high-k material, whereas the gate insulation layer (231) of the field effect transistor (250) is formed of an ultra thin oxide layer or oxynitride layer so as to provide for superior carrier mobility at the interface between the gate insulation layer and the underlying channel region. Since carrier mobility in the capacitor is not of great importance, the high-k material allows the provision of high capacitance per unit area while featuring a thickness sufficient to effectively reduce leakage current.

公开(公告)号：EP1535316A1

公开(公告)日：2005-06-01

申请号：EP03752145.7

申请日：2003-08-29

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： WIECZOREK, Karsten ,  RADEHAUS, Christian

IPC: H01L21/28 ,  H01L29/51

CPC classification number: H01L21/28185 ,  H01L21/28194 ,  H01L21/31604 ,  H01L21/31612 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: A field effect transistor 300 comprises a gate insulation layer including an anisotropic dielectric 305. The orientation is selected such that a first permittivity parallel to the gate insulation layer is significantly less than a second permittivity perpendicular to the gate insulation layer.