公开(公告)号：WO2015187329A1

公开(公告)日：2015-12-10

申请号：PCT/US2015/030731

申请日：2015-05-14

Applicant: APPLE INC.

Inventor： TRIPATHI, Brijesh ,  AGARWAL, Manu ,  HOLLAND, Peter F.

IPC: G06F3/041

CPC classification number: G06F3/0412 ,  G06F3/0416 ,  G06F2203/04101 ,  G06T1/20 ,  H04N3/24 ,  H04N2101/00

Abstract: Systems, apparatuses, and methods for performing mid-frame blanking. A first portion of a frame is driven to a display and then a first mid-frame blanking interval is generated. Following this first mid-frame blanking interval, a second portion of the frame is driven to the display, followed by a second mid-frame blanking interval, followed by a third portion of the frame, and so on. Any number of mid-frame blanking intervals may be introduced in a given frame. During each mid-frame blanking interval, touch sensing is performed to detect touch events on the screen for in-cell touch type displays. For displays with touch sensors electrically separated from the display common voltage layer, special sense scan steps are performed during mid-frame blanking intervals. By performing touch sensing or special sense scan steps during a frame rather than only at the end of a frame, the performance of touch sensing is improved.

Abstract translation: 执行中帧消隐的系统，设备和方法。 帧的第一部分被驱动到显示器，然后产生第一中间帧消隐间隔。 在该第一中间帧消隐间隔之后，帧的第二部分被驱动到显示器，随后是第二中间帧消隐间隔，随后是帧的第三部分，等等。 可以在给定的帧中引入任何数量的中帧消隐间隔。 在每个中间帧消隐间隔期间，执行触摸感测以检测用于小区内触摸式显示的屏幕上的触摸事件。 对于具有与显示器公共电压层电气分离的触摸传感器的显示器，在中帧消隐间隔期间执行特殊感测扫描步骤。 通过在帧期间执行触摸感测或特殊感测扫描步骤，而不仅仅是在帧的结尾处，提高了触摸感测的性能。

公开(公告)号：WO2015047658A1

公开(公告)日：2015-04-02

申请号：PCT/US2014/053377

申请日：2014-08-29

Applicant: APPLE INC.

Inventor： GREEMEBAUM, Kenneth ,  HENDRY, Ian ,  OLLMAN, Ian ,  HAYWARD, David ,  TRIPATHI, Brijesh

IPC: G11B27/034 ,  H04N19/30 ,  H04N21/2343 ,  H04N21/845 ,  H04N21/2662

CPC classification number: H04N19/85 ,  G06T9/00 ,  G11B27/034 ,  H04N19/186 ,  H04N19/30 ,  H04N19/33 ,  H04N19/463 ,  H04N21/234327 ,  H04N21/2662 ,  H04N21/845

Abstract: Techniques are provided for encoding an extended image such that it is backwards compatible with existing decoding devices. An extended image format is defined such that the extended image format is consistent with an existing image format over the full range of the existing image format. Because the extended image format is consistent with the existing image format over the full range of the existing image format, additional image information that is included in an extended image can be extracted from the extended image. A base version of an image (expressed using the existing image format) may be encoded in a payload portion and the extracted additional information may be stored in a metadata portion of a widely supported image file format.

Abstract translation: 提供了用于对扩展图像进行编码的技术，使得其与现有的解码装置向后兼容。 定义扩展图像格式，使得扩展图像格式与现有图像格式的全部范围内的现有图像格式一致。 由于扩展图像格式与现有图像格式的全部范围内的现有图像格式一致，所以可以从扩展图像中提取包括在扩展图像中的附加图像信息。 图像的基本版本（使用现有图像格式表示）可以被编码在有效载荷部分中，并且所提取的附加信息可以存储在广泛支持的图像文件格式的元数据部分中。

公开(公告)号：WO2015020773A1

公开(公告)日：2015-02-12

申请号：PCT/US2014/047027

申请日：2014-07-17

Applicant: APPLE INC.

Inventor： HOLLAND, Peter F. ,  TRIPATHI, Brijesh

IPC: G06T9/00

CPC classification number: G09G5/006 ,  G06T3/4092 ,  G06T9/00 ,  G09G2340/02 ,  G09G2340/0407 ,  H04N19/124 ,  H04N19/134 ,  H04N19/182 ,  H04N19/184 ,  H04N19/186 ,  H04N19/90

Abstract: A method and device for data compression are presented, in which a data processor may receive a packet of image data which includes four groups of N bits, where N is an integer greater than 2. The data processor may compress the received packet of data, such that a total number of bits for the converted packet is less than four times N. The data processor may compress the received packet of image data by reducing the resolution of three of the values while maintaining the resolution of the fourth value. To reduce the resolution of the three values, the data processor may apply a dithering formula to the values. The data processor may then send the converted packet via an interface.

Abstract translation: 提出了一种用于数据压缩的方法和装置，其中数据处理器可以接收包括四个N位组的图像数据分组，其中N是大于2的整数。数据处理器可以压缩所接收的数据分组， 使得转换的分组的总比特数小于N倍。数据处理器可以通过在保持第四值的分辨率的同时降低三个值的分辨率来压缩接收的图像数据分组。 为了降低三个值的分辨率，数据处理器可以对该值应用抖动公式。 然后，数据处理器可以经由接口发送转换的分组。

公开(公告)号：WO2014099911A1

公开(公告)日：2014-06-26

申请号：PCT/US2013/075665

申请日：2013-12-17

Applicant: APPLE INC.

Inventor： TRIPATHI, Brijesh

IPC: G09G5/00 ,  G09G5/12

CPC classification number: G06F1/12 ,  G09G5/006 ,  G09G5/008 ,  G09G5/12 ,  G09G2330/021 ,  G09G2340/0435 ,  G09G2360/18 ,  G09G2370/047 ,  G09G2370/10

Abstract: Embodiments of an apparatus for implementing a display port interface are disclosed. The apparatus may include a source processor and a sink processor coupled through an interface. The interface may include a primary link, an auxiliary link, and a hot plug detect link. The source processor may be operable to send a wake-up command to the sink processor via the auxiliary link. The source processor may send initialization parameters to the sink processor via the primary link. The initialization parameters may include a clock data recovery lock parameter and an idle parameter. Following the initialization parameters, the source processor may send a synchronization signal to the sink processor via the primary link. The source processor may then send a sleep command via the primary link to the sink processor.

Abstract translation: 公开了一种用于实现显示端口接口的设备的实施例。 该装置可以包括通过接口耦合的源处理器和宿处理器。 接口可以包括主链路，辅助链路和热插拔检测链路。 源处理器可以用于经由辅助链路向宿处理器发送唤醒命令。 源处理器可以经由主链路将初始化参数发送到宿处理器。 初始化参数可以包括时钟数据恢复锁定参数和空闲参数。 在初始化参数之后，源处理器可以经由主链路向宿处理器发送同步信号。 然后，源处理器可以经由主链路向宿处理器发送睡眠命令。

公开(公告)号：WO2013152123A2

公开(公告)日：2013-10-10

申请号：PCT/US2013/035150

申请日：2013-04-03

Applicant: APPLE INC.

Inventor： TRIPATHI, Brijesh ,  GUILLOU, Jean-Pierre S.

IPC: G09G3/20

CPC classification number: G06F3/041 ,  G06T19/006 ,  G09G3/20 ,  G09G2320/029 ,  G09G2320/0606 ,  G09G2320/0613 ,  G09G2320/103 ,  G09G2330/02 ,  G09G2330/021 ,  G09G2340/0435 ,  G09G2354/00 ,  G09G2360/18

Abstract: An electronic device may be provided with a display. The display may be a variable frame rate display capable of adaptively adjusting a frame rate at which display frames are displayed in response to information associated with the current state of operation of the device. The information may be gathered using control circuitry in the electronic device. The control circuitry may gather the information for adjusting the frame rate by monitoring the electronic device power supply configuration, other device components, the type of content to be displayed, and user-input signals. The control circuitry may adjust the frame rate based on the gathered information by increasing or decreasing the frame rate. The control circuitry may be formed as a portion of display control circuitry for the device such as a display driver integrated circuit or may be formed as a portion of storage and processing circuitry external to the display.

Abstract translation: 电子设备可以设置有显示器。 显示器可以是可变帧频显示器，其能够响应于与设备的当前操作状态相关联的信息自适应地调整显示显示帧的帧速率。 信息可以使用电子设备中的控制电路来收集。 控制电路可通过监视电子设备电源配置，其他设备组件，要显示的内容的类型以及用户输入信号来收集用于调整帧速率的信息。 控制电路可以通过增加或减少帧速率来基于收集的信息来调整帧速率。 控制电路可以形成为用于诸如显示驱动器集成电路之类的设备的显示控制电路的一部分，或者可以形成为显示器外部的存储和处理电路的一部分。

公开(公告)号：WO2012170274A1

公开(公告)日：2012-12-13

申请号：PCT/US2012/040151

申请日：2012-05-31

Applicant: Apple Inc. ,  MILLET, Timothy, John ,  TRIPATHI, Brijesh ,  HOLLAND, Peter, F.

Inventor： MILLET, Timothy, John ,  TRIPATHI, Brijesh ,  HOLLAND, Peter, F.

IPC: G06T3/40

CPC classification number: G06T3/4007

Abstract: A scaling unit is disclosed that is within a computing device having an internal display and an external interface. The scaling unit facilitates the concurrent presentation of images on the internal display and an external display connected to the external interface. In configurations in which the external interface does not have sufficient data width to concurrently display images on the external display at the same resolution as the internal display, the scaling unit may be used to reduce the number of pixels in a line, thus reducing bandwidth requirements at the external interface. The scaling unit may also scale further to maintain an aspect ratio of the image displayed on the internal display. Further vertical scaling may be performed outside the computing device (e.g., by a dongle coupled between the computing device and the external display), such that the scaling unit may be implemented with reduced memory requirements.

Abstract translation: 公开了一种在具有内部显示器和外部接口的计算设备内的缩放单元。 缩放单元便于在内部显示器上同时呈现图像，并且外部显示器连接到外部接口。 在外部接口不具有足够的数据宽度以与外部显示器以与内部显示器相同的分辨率同时显示图像的配置中，缩放单元可以用于减少一行中的像素数量，从而降低带宽需求 在外部接口。 缩放单元还可以进一步缩放以保持在内部显示器上显示的图像的纵横比。 可以在计算设备外部（例如，通过耦合在计算设备和外部显示器之间的加密狗）进行进一步的垂直缩放，使得缩放单元可以以减少的存储器要求来实现。

公开(公告)号：EP3146408B1

公开(公告)日：2018-11-28

申请号：EP15716364.3

申请日：2015-04-01

Applicant: Apple Inc.

Inventor： TRIPATHI, Brijesh ,  KEIL, Shane, J. ,  GULATI, Manu ,  CHO, Jung Wook ,  MACHNICKI, Erik, P. ,  HERBECK, Gilbert, H. ,  MILLET, Timothy, J. ,  DE CESARE, Joshua, P. ,  DALAL, Anand

IPC: G06F1/32 ,  G06F13/16

CPC classification number: G01D9/00 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/3293 ,  G06F13/1689 ,  Y02D10/122 ,  Y02D10/171 ,  Y02D50/20

Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

公开(公告)号：EP3146408A1

公开(公告)日：2017-03-29

申请号：EP15716364.3

申请日：2015-04-01

Applicant: Apple Inc.

Inventor： TRIPATHI, Brijesh ,  KEIL, Shane J. ,  GULATI, Manu ,  CHO, Jung Wook ,  MACHNICKI, Erik P. ,  HERBECK, Gilbert H. ,  MILLET, Timothy J. ,  DE CESARE, Joshua P. ,  DALAL, Anand

IPC: G06F1/32

CPC classification number: G01D9/00 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/3293 ,  G06F13/1689 ,  Y02D10/122 ,  Y02D10/171 ,  Y02D50/20

Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

Abstract translation: 在一个实施例中，芯片上的系统（SOC）包括当SOC的其余部分断电时保持供电的组件。 该组件可以包括用于从各种设备传感器捕获数据的传感器捕获单元，并且可以过滤所捕获的传感器数据。 响应于过滤，组件可以唤醒SOC的剩余部分以允许处理。 组件可以存储可编程配置数据，与SOC最近断电时的状态相匹配，用于SOC的其他组件，以便在唤醒后重新编程它们。 在一些实施例中，组件可以被配置为唤醒SOC内的存储器控​​制器和到存储器控制器的路径，以便将数据写入存储器。 SOC的其余部分可能仍然断电。

公开(公告)号：EP2909830A1

公开(公告)日：2015-08-26

申请号：EP13818605.1

申请日：2013-12-17

Applicant: Apple Inc.

Inventor： TRIPATHI, Brijesh

IPC: G09G3/20 ,  G09G5/00 ,  G09G5/12 ,  G09G5/36

CPC classification number: G09G5/008 ,  G06T1/20 ,  G06T2200/28 ,  G09G3/2096 ,  G09G5/003 ,  G09G5/006 ,  G09G5/12 ,  G09G5/363 ,  G09G2320/103 ,  G09G2330/02 ,  G09G2360/18 ,  G09G2370/04 ,  G09G2370/10 ,  G09G2370/12 ,  H04J3/0667 ,  H04N21/4302 ,  H04N21/4305

Abstract: Embodiments of an apparatus (200) for implementing a display port interface (211) are disclosed. The apparatus may include a source processor (203) and a sink processor (209) coupled through an interface (211). The sink processor (209) may be operable to send a synchronization signal to the source processor (203) through the interface (211). The source processor (203) may be operable, dependent upon the synchronization signal, to send data to the sink processor (209).

公开(公告)号：EP2795583A1

公开(公告)日：2014-10-29

申请号：EP13706371.5

申请日：2013-02-12

Applicant: Apple Inc.

Inventor： OKRUHLICA, Craig M. ,  TRIPATHI, Brijesh ,  BHARGAVA, Nitin

IPC: G06T15/50 ,  G09G5/36 ,  G06T15/00 ,  G06F1/32

CPC classification number: G09G5/363 ,  G06F1/325 ,  G06T1/20 ,  G06T17/00 ,  G06T2210/32 ,  G09G2330/021 ,  G09G2340/10

Abstract: A graphics processing circuit and method for power savings in the same is disclosed. In one embodiment, a graphics processing circuit includes a number of channels. The number of channels includes a number of color component channels that are each configured to process color components of pixel values of an incoming frame of graphics information. The number of channels also includes an alpha scaling channel configured to process alpha values (indicative of a level of transparency) for the incoming and/or outgoing frames. The graphics processing circuit also includes a control circuit. The control circuit is configured to place the alpha scaling channel into a low-power state responsive to determining that at least one of the incoming or outgoing frames does not include alpha values.

Abstract translation: 公开了一种用于省电的图形处理电路和方法。 在一个实施例中，图形处理电路包括多个通道。 通道数量包括多个颜色分量通道，每个颜色分量通道被配置为处理进入的图形信息帧的像素值的颜色分量。 频道数量还包括被配置为处理传入和/或输出帧的alpha值（指示透明度水平）的α缩放通道。 图形处理电路还包括控制电路。 控制电路被配置为响应于确定进入或输出帧中的至少一个不包括阿尔法值，将阿尔法缩放通道置于低功率状态。