公开(公告)号：WO2023034036A1

公开(公告)日：2023-03-09

申请号：PCT/US2022/040767

申请日：2022-08-18

Applicant: APPLE INC.

Inventor： MATHEWS, Gregory S. ,  KEIL, Shane J.

IPC: G06F3/06

Abstract: Techniques for scheduling memory operations are disclosed in which alternate read/write commands within a multi-bank memory operation are delayed beyond a minimum timing parameter in order to increase memory data bus utilization. The remaining read/write commands are not delayed beyond the minimum timing parameter. Every other clock cycle (e.g., even clock cycles) within the memory operation is reserved for activate commands, while other commands such as sync and read/write are scheduled on the intervening clock cycles (e.g., odd clock cycles). For memory devices for which a sync command (which causes a clock of the memory data bus to start) is to precede a corresponding read/write command by a number of clock cycles that would place it in a cycle reserved for activate commands, a particular operation mode is disclosed in which the memory device internally delays a received sync command.

公开(公告)号：WO2014113466A1

公开(公告)日：2014-07-24

申请号：PCT/US2014/011673

申请日：2014-01-15

Applicant: APPLE INC.

Inventor： KEIL, Shane J. ,  MACHNICKI, Erik P. ,  DE CESARE, Josh P.

IPC: G06F1/32

CPC classification number: G06F1/3234 ,  G06F1/3203

Abstract: Techniques are disclosed relating to power management within an integrated circuits. In one embodiment an apparatus is disclosed that includes a circuit and a power management unit. The power management unit is configured to provide, based on a programmable setting, an indication of whether an attempted communication to the circuit is permitted to cause the circuit to exit from a power-managed state. In some embodiments, the apparatus includes a fabric configured to transmit the attempted communication to the circuit from a device. In such an embodiment, the circuit is configured to exit the power-managed state in response to receiving the attempted communication. The fabric is configured to determine whether to transmit the attempted communication based on the indication provided by the power management unit.

Abstract translation: 公开了与集成电路内的电力管理有关的技术。 在一个实施例中，公开了一种包括电路和电源管理单元的装置。 功率管理单元被配置为基于可编程设置来提供是否允许对电路的尝试通信是使电路退出功率管理状态的指示。 在一些实施例中，该装置包括被配置成从设备将尝试的通信传送到电路的结构。 在这样的实施例中，电路被配置为响应于接收到尝试的通信而退出功率管理状态。 结构被配置为基于由电力管理单元提供的指示来确定是否发送尝试的通信。

公开(公告)号：WO2014100152A1

公开(公告)日：2014-06-26

申请号：PCT/US2013/076075

申请日：2013-12-18

Applicant: APPLE INC.

Inventor： MACHNICKI, Erik P. ,  SAUND, Gurjeet S. ,  FUKAMI, Munetoshi ,  KEIL, Shane J.

IPC: G06F1/32

CPC classification number: G05B11/01 ,  G06F1/3237 ,  G06F1/3253 ,  Y02D10/128 ,  Y02D10/151 ,  Y02D50/20

Abstract: A method and apparatus for dynamic clock and power gating and decentralized wakeups is disclosed. In one embodiment, an integrated circuit (IC) includes power-manageable functional units and a power management unit. Each of the power manageable functional units is configured to convey a request to enter a low power state to the power management unit The power management unit may respond by causing a requesting functional unit to enter the low power state. Should another functional unit initiate a request to communicate with a functional unit currently in the low power state, it may send a request to that functional unit. The receiving functional unit may respond to the request by exiting the low power state and resuming operation in the active state.

Abstract translation: 公开了一种用于动态时钟和电源门控和分散式唤醒的方法和装置。 在一个实施例中，集成电路（IC）包括功率可管理的功能单元和电源管理单元。 每个功率可管理功能单元被配置为向电力管理单元传送进入低功率状态的请求。电源管理单元可以通过使请求功能单元进入低功率状态来进行响应。 如果另一个功能单元发起与当前处于低功率状态的功能单元通信的请求，则它可以向该功能单元发送请求。 接收功能单元可以通过退出低功率状态并在活动状态下恢复运行来响应该请求。

公开(公告)号：EP3146408A1

公开(公告)日：2017-03-29

申请号：EP15716364.3

申请日：2015-04-01

Applicant: Apple Inc.

Inventor： TRIPATHI, Brijesh ,  KEIL, Shane J. ,  GULATI, Manu ,  CHO, Jung Wook ,  MACHNICKI, Erik P. ,  HERBECK, Gilbert H. ,  MILLET, Timothy J. ,  DE CESARE, Joshua P. ,  DALAL, Anand

IPC: G06F1/32

CPC classification number: G01D9/00 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/3293 ,  G06F13/1689 ,  Y02D10/122 ,  Y02D10/171 ,  Y02D50/20

Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

Abstract translation: 在一个实施例中，芯片上的系统（SOC）包括当SOC的其余部分断电时保持供电的组件。 该组件可以包括用于从各种设备传感器捕获数据的传感器捕获单元，并且可以过滤所捕获的传感器数据。 响应于过滤，组件可以唤醒SOC的剩余部分以允许处理。 组件可以存储可编程配置数据，与SOC最近断电时的状态相匹配，用于SOC的其他组件，以便在唤醒后重新编程它们。 在一些实施例中，组件可以被配置为唤醒SOC内的存储器控​​制器和到存储器控制器的路径，以便将数据写入存储器。 SOC的其余部分可能仍然断电。