公开(公告)号：WO2017099861A1

公开(公告)日：2017-06-15

申请号：PCT/US2016/051967

申请日：2016-09-15

Applicant: APPLE INC.

Inventor： YU, Shu-Yi ,  MACHNICKI, Erik P. ,  HERBECK, Gilbert H. ,  KATTEL, Kiran B. ,  GULATI, Manu

IPC: G06F1/12 ,  G06F1/14

CPC classification number: G06F1/12 ,  G06F1/14

Abstract: In an embodiment, an integrated circuit such as an SOC (or even a discrete chip system) includes one or more local timebases in various locations. The timebases may be incremented based on a high frequency local clock that may be subject to variation during use due. Periodically, based on a lower frequency clock that is subject to less variation, the local timebases may be synchronized to the correct time, using hardware circuitry. In particular, the correct timebase value for the next synchronization may be transmitted to each local timebase, and the control circuit for the local timebase may be configured to saturate the local timebase at the correct value if the local timebase reaches the correct value before the synchronization occurs. Similarly, if the synchronization occurs and the local timebase has not reached the correct value, the control circuit may be configured to load the correct timebase value.

Abstract translation: 在一个实施例中，诸如SOC（或者甚至是分立芯片系统）的集成电路在各个位置包括一个或多个本地时基。 时基可以基于在使用期间可能经历变化的高频本地时钟而增加。 周期性地，基于变化较小的较低频率的时钟，可以使用硬件电路将本地时基同步到正确的时间。 特别地，如果在同步之前本地时基达到正确值，则可以将用于下一同步的正确时基值传送给每个本地时基，并且可以将用于本地时基的控制电路配置为使本地时基饱和为正确的值 发生。 类似地，如果发生同步并且本地时基尚未达到正确值，则可以将控制电路配置为加载正确的时基值。

公开(公告)号：WO2016130212A1

公开(公告)日：2016-08-18

申请号：PCT/US2015/066310

申请日：2015-12-17

Applicant: APPLE INC.

Inventor： GULATI, Manu ,  HERBECK, Gilbert H. ,  KOSUT, Alexei E. ,  JONES, Girault W. ,  MILLET, Timothy J.

IPC: G10L25/78 ,  G06F3/16 ,  G10L15/28

CPC classification number: G10L15/28 ,  G10L15/08 ,  G10L15/22 ,  G10L2015/088 ,  G10L2015/223

Abstract: In an embodiment, a system on a chip (SOC) may include one or more central processing units (CPUs), a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples and match those audio samples against a predetermined pattern. The circuit may operate according to a first clock during the time that the rest of the SOC is powered down. In response to detecting the predetermined pattern in the samples, the circuit may cause the memory controller and processors to power up. During the power up process, a second clock having one or more better characteristics than the first clock may become available. The circuit may switch to the second clock while preserving the samples, or losing at most one sample, or no more than a threshold number of samples.

Abstract translation: 在一个实施例中，芯片上的系统（SOC）可以包括一个或多个中央处理单元（CPU），存储器控制器和被配置为当SOC的其余部分断电时保持通电的电路。 该电路可以被配置为接收音频采样并将这些音频样本与预定模式相匹配。 在SOC的其余部分断电的时间内，电路可以根据第一时钟进行操作。 响应于检测样本中的预定模式，电路可以使存储器控制器和处理器加电。 在上电过程中，具有比第一时钟具有一个或多个更好特征的第二时钟可以变得可用。 电路可以切换到第二时钟，同时保持采样，或者丢失至多一个采样，或者不超过阈值数量的采样。

公开(公告)号：EP3146408A1

公开(公告)日：2017-03-29

申请号：EP15716364.3

申请日：2015-04-01

Applicant: Apple Inc.

Inventor： TRIPATHI, Brijesh ,  KEIL, Shane J. ,  GULATI, Manu ,  CHO, Jung Wook ,  MACHNICKI, Erik P. ,  HERBECK, Gilbert H. ,  MILLET, Timothy J. ,  DE CESARE, Joshua P. ,  DALAL, Anand

IPC: G06F1/32

CPC classification number: G01D9/00 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/3293 ,  G06F13/1689 ,  Y02D10/122 ,  Y02D10/171 ,  Y02D50/20

Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

Abstract translation: 在一个实施例中，芯片上的系统（SOC）包括当SOC的其余部分断电时保持供电的组件。 该组件可以包括用于从各种设备传感器捕获数据的传感器捕获单元，并且可以过滤所捕获的传感器数据。 响应于过滤，组件可以唤醒SOC的剩余部分以允许处理。 组件可以存储可编程配置数据，与SOC最近断电时的状态相匹配，用于SOC的其他组件，以便在唤醒后重新编程它们。 在一些实施例中，组件可以被配置为唤醒SOC内的存储器控​​制器和到存储器控制器的路径，以便将数据写入存储器。 SOC的其余部分可能仍然断电。

公开(公告)号：EP3257045A1

公开(公告)日：2017-12-20

申请号：EP15882269.2

申请日：2015-12-17

Applicant: Apple Inc.

Inventor： GULATI, Manu ,  HERBECK, Gilbert H. ,  KOSUT, Alexei E. ,  JONES, Girault W. ,  MILLET, Timothy J.

IPC: G10L25/78 ,  G06F3/16 ,  G10L15/28

CPC classification number: G10L15/28 ,  G10L15/08 ,  G10L15/22 ,  G10L2015/088 ,  G10L2015/223

Abstract: In an embodiment, a system on a chip (SOC) may include one or more central processing units (CPUs), a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples and match those audio samples against a predetermined pattern. The circuit may operate according to a first clock during the time that the rest of the SOC is powered down. In response to detecting the predetermined pattern in the samples, the circuit may cause the memory controller and processors to power up. During the power up process, a second clock having one or more better characteristics than the first clock may become available. The circuit may switch to the second clock while preserving the samples, or losing at most one sample, or no more than a threshold number of samples.

公开(公告)号：EP3257045B1

公开(公告)日：2019-06-05

申请号：EP15882269.2

申请日：2015-12-17

Applicant: Apple Inc.

Inventor： GULATI, Manu ,  HERBECK, Gilbert H. ,  KOSUT, Alexei E. ,  JONES, Girault W. ,  MILLET, Timothy J.

IPC: G10L15/22 ,  G10L15/08