公开(公告)号：WO2016130212A1

公开(公告)日：2016-08-18

申请号：PCT/US2015/066310

申请日：2015-12-17

Applicant: APPLE INC.

Inventor： GULATI, Manu ,  HERBECK, Gilbert H. ,  KOSUT, Alexei E. ,  JONES, Girault W. ,  MILLET, Timothy J.

IPC: G10L25/78 ,  G06F3/16 ,  G10L15/28

CPC classification number: G10L15/28 ,  G10L15/08 ,  G10L15/22 ,  G10L2015/088 ,  G10L2015/223

Abstract: In an embodiment, a system on a chip (SOC) may include one or more central processing units (CPUs), a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples and match those audio samples against a predetermined pattern. The circuit may operate according to a first clock during the time that the rest of the SOC is powered down. In response to detecting the predetermined pattern in the samples, the circuit may cause the memory controller and processors to power up. During the power up process, a second clock having one or more better characteristics than the first clock may become available. The circuit may switch to the second clock while preserving the samples, or losing at most one sample, or no more than a threshold number of samples.

Abstract translation: 在一个实施例中，芯片上的系统（SOC）可以包括一个或多个中央处理单元（CPU），存储器控制器和被配置为当SOC的其余部分断电时保持通电的电路。 该电路可以被配置为接收音频采样并将这些音频样本与预定模式相匹配。 在SOC的其余部分断电的时间内，电路可以根据第一时钟进行操作。 响应于检测样本中的预定模式，电路可以使存储器控制器和处理器加电。 在上电过程中，具有比第一时钟具有一个或多个更好特征的第二时钟可以变得可用。 电路可以切换到第二时钟，同时保持采样，或者丢失至多一个采样，或者不超过阈值数量的采样。

公开(公告)号：WO2013036639A1

公开(公告)日：2013-03-14

申请号：PCT/US2012/053963

申请日：2012-09-06

Applicant: APPLE INC. ,  MILLET, Timothy J. ,  KANCHANA, Muditha ,  DESAI, Shailendra S.

Inventor： MILLET, Timothy J. ,  KANCHANA, Muditha ,  DESAI, Shailendra S.

IPC: G06F15/17

CPC classification number: G06F13/4022 ,  Y02D10/14 ,  Y02D10/151

Abstract: A system, apparatus, and method for routing traffic in a SoC from I/O devices to memory. A coherence switch routes coherent traffic through a coherency port on a processor complex to a real-time port of a memory controller. The coherence switch routes non-coherent traffic to a non-real time port of the memory controller. The coherence switch can also dynamically switch traffic between the two paths. The routing of traffic can be configured via a configuration register, and while software can initiate an update to the configuration register, the actual coherence switch hardware will implement the update. Software can write to a software-writeable copy of the configuration register to initiate an update to the flow path to memory for a transaction identifier. The coherence switch detects the update to the software-writeable copy, and then the coherence switch updates the working copy of the configuration register and implements the new routing.

Abstract translation: 用于将SoC中的业务从I / O设备路由到存储器的系统，装置和方法。 相干切换器将相干流量通过处理器复合体上的一致端口路由到存储器控制器的实时端口。 相干切换将非相干流量路由到存储器控制器的非实时端口。 相干切换器还可以动态地切换两条路径之间的流量。 流量路由可以通过配置寄存器配置，而软件可以启动对配置寄存器的更新，实际的相干交换机硬件将实现更新。 软件可以写入配置寄存器的可写入软件的副本，以启动对事务标识符的存储器流程的更新。 相干开关检测到软件可写入副本的更新，然后相干开关更新配置寄存器的工作副本并实现新的路由。

公开(公告)号：WO2016033254A1

公开(公告)日：2016-03-03

申请号：PCT/US2015/047058

申请日：2015-08-26

Applicant: APPLE INC.

Inventor： CHENG, Joseph J. ,  MILLET, Timothy J. ,  GO, Shun Wai ,  COTE, Guy

IPC: H04N19/129 ,  G06F9/46 ,  G06F9/48 ,  H04N19/127 ,  H04N19/174 ,  H04N19/42 ,  H04N19/40

CPC classification number: H04N19/176 ,  G06F9/461 ,  G06F9/4818 ,  H04N19/127 ,  H04N19/129 ,  H04N19/172 ,  H04N19/174 ,  H04N19/182 ,  H04N19/40 ,  H04N19/42 ,  H04N19/46

Abstract: A context switching method for video encoders that enables higher priority video streams to interrupt lower priority video streams. A high priority frame may be received for processing while another frame is being processed. The pipeline may be signaled to perform a context stop for the current frame. The pipeline stops processing the current frame at an appropriate place, and propagates the stop through the stages of the pipeline and to a transcoder through DMA. The stopping location is recorded. The video encoder may then process the higher-priority frame. When done, a context restart is performed and the pipeline resumes processing the lower-priority frame beginning at the recorded location. The transcoder may process data for the interrupted frame while the higher-priority frame is being processed in the pipeline, and similarly the pipeline may begin processing the lower-priority frame after the context restart while the transcoder completes processing the higher-priority frame.

Abstract translation: 一种视频编码器的上下文切换方法，其使得较高优先级的视频流能够中断较低优先级的视频流。 当处理另一帧时，可以接收高优先级帧以进行处理。 可以用信号通知流水线以执行当前帧的上下文停止。 流水线在适当的位置停止处理当前帧，并通过流水线传播停止点，并通过DMA传播到代码转换器。 记录停止位置。 视频编码器然后可以处理较高优先级的帧。 完成后，执行上下文重新启动，并且流水线从记录的位置恢复处理较低优先级的帧。 代码转换器可以在流水线中处理较高优先级帧的同时处理中断帧的数据，类似地，当代码转换器完成处理较高优先级帧时，流水线可以在上下文重新启动之后开始处理较低优先级的帧。

公开(公告)号：WO2015073124A1

公开(公告)日：2015-05-21

申请号：PCT/US2014/057599

申请日：2014-09-26

Applicant: APPLE INC.

Inventor： SILVERSTEIN, D. Amnon ,  GO, Shun Wai ,  LIM, Suk Hwan ,  MILLET, Timothy J. ,  CHEN, Ting ,  NI, Bin

IPC: H04N7/01 ,  H04N5/232

CPC classification number: H04N5/23245 ,  H04N1/212 ,  H04N5/23216 ,  H04N5/23232 ,  H04N5/23293 ,  H04N7/0122 ,  H04N9/87

Abstract: In an embodiment, an electronic device may be configured to capture still frames during video capture, but may capture the still frames in the 4x3 aspect ratio and at higher resolution than the 16x9 aspect ratio video frames. The device may interleave high resolution, 4x3 frames and lower resolution 16x9 frames in the video sequence, and may capture the nearest higher resolution, 4x3 frame when the user indicates the capture of a still frame. Alternatively, the device may display 16x9 frames in the video sequence, and then expand to 4x3 frames when a shutter button is pressed. The device may capture the still frame and return to the 16x9 video frames responsive to a release of the shutter button.

Abstract translation: 在一个实施例中，电子设备可以被配置为在视频捕获期间捕获静止帧，但是可以以4×3宽高比捕获静止帧，并且以比16×9宽高比视频帧更高的分辨率捕获静止帧。 该装置可以在视频序列中交错高分辨率，4×3帧和较低分辨率的16×9帧，并且当用户指示拍摄静止帧时可以捕获最接近的更高分辨率的4×3帧。 或者，设备可以在视频序列中显示16x9帧，然后当按下快门按钮时，扩展为4x3帧。 该装置可以捕获静止帧并响应于快门按钮的释放而返回16×9视频帧。

公开(公告)号：WO2013074200A1

公开(公告)日：2013-05-23

申请号：PCT/US2012/056857

申请日：2012-09-24

Applicant: APPLE INC. ,  TRIPATHI, Brijesh ,  MILLET, Timothy J.

Inventor： TRIPATHI, Brijesh ,  MILLET, Timothy J.

IPC: H04N5/05

CPC classification number: G06F1/08 ,  H04B15/06

Abstract: A method and apparatus for changing a frequency of a clock signal to avoid interference is disclosed. In one embodiment, data conveyed on a first interface is synchronized to a clock signal at a first frequency. Signals are conveyed on a second interface at another frequency. Responsive to a change of the frequency at which signals are conveyed on a second interface, a clock control unit associated with the first interface initiates a change of the clock signal to a second frequency. The second frequency may be chosen as to not cause interference with the frequency at which signals are conveyed on the second interface. The change of the clock frequency may be performed in such a manner as to prevent spurious activity on the clock line of the interface.

Abstract translation: 公开了一种用于改变时钟信号的频率以避免干扰的方法和装置。 在一个实施例中，在第一接口上传送的数据与第一频率的时钟信号同步。 信号在另一个频率的第二个接口上传送。 响应于在第二接口上传送信号的频率的变化，与第一接口相关联的时钟控制单元启动时钟信号的变化到第二频率。 第二频率可以被选择为不引起对在第二接口上传送信号的频率的干扰。 时钟频率的改变可以以防止对接口的时钟线的虚假活动的方式来执行。

公开(公告)号：WO2012050773A1

公开(公告)日：2012-04-19

申请号：PCT/US2011/052599

申请日：2011-09-21

Applicant: APPLE INC. ,  MILLET, Timothy J. ,  MACHNICKI, Erik P. ,  BALKAN, Deniz ,  GUPTA, Vijay

Inventor： MILLET, Timothy J. ,  MACHNICKI, Erik P. ,  BALKAN, Deniz ,  GUPTA, Vijay

IPC: G06F1/26

CPC classification number: G06F1/3203 ,  G06F1/3275 ,  G06F1/3287 ,  G06F12/0802 ,  G06F2212/1028 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/171 ,  Y02D50/20

Abstract: In an embodiment, a control circuit is configured to transmit operations to a circuit block that is being powered up after being powered down, to reinitialize the circuit block for operation. The operations may be stored in a memory (e.g. a set of registers) to which the control circuit is coupled. In an embodiment, the control circuit may also be configured to transmit other operations from the memory to the circuit block prior to the circuit block being powered down. Accordingly, the circuit block may be powered up or powered down even during times that the processors in the system are powered down (and thus software is not executable at the time), without waking the processors for the power up/power down event. In an embodiment, the circuit block may be a cache coupled to the one or more processors.

Abstract translation: 在一个实施例中，控制电路被配置为向断电后正在上电的电路块传送操作，以重新初始化电路块以进行操作。 操作可以存储在控制电路耦合到的存储器（例如一组寄存器）中。 在一个实施例中，控制电路还可以被配置为在电路块断电之前将其他操作从存储器传送到电路块。 因此，即使在系统中的处理器断电（并且因此软件不可执行的时候），即使在唤醒处理器以进行上电/断电事件的时间内，电路块也可以上电或掉电。 在一个实施例中，电路块可以是耦合到一个或多个处理器的高速缓存器。

公开(公告)号：WO2017023420A1

公开(公告)日：2017-02-09

申请号：PCT/US2016/036688

申请日：2016-06-09

Applicant: APPLE INC.

Inventor： MILLET, Timothy J. ,  GULATI, Manu ,  SPENCE, Arthur L. ,  SAUND, Gurjeet S. ,  ESSER, Robert P.

IPC: G06F9/48

CPC classification number: G06T1/20 ,  G06F9/4893 ,  G06F9/52 ,  G06T1/60 ,  G09G5/001 ,  G09G5/363 ,  G09G2360/08 ,  Y02D10/24

Abstract: An embodiment of a system may include a plurality of media units, a processor, and circuitry. Each media unit may be configured to execute one or more commands to process a display image. The processor may be configured to store a plurality of media processing commands in a queue. The circuitry may be configured to retrieve a first media processing command from the queue and send the first media processing command to a first media unit. The circuitry may also be configured to retrieve a second media processing from the queue and send the second media processing command to a second media unit in response to receiving an interrupt from the first media unit. The circuitry may then copy data from the first media unit to the second media unit in response to receiving the interrupt from the first media unit.

Abstract translation: 系统的实施例可以包括多个媒体单元，处理器和电路。 每个媒体单元可以被配置为执行一个或多个命令来处理显示图像。 处理器可以被配置为在队列中存储多个媒体处理命令。 电路可以被配置为从队列检索第一媒体处理命令，并将第一媒体处理命令发送到第一媒体单元。 电路还可以被配置为响应于从第一媒体单元接收到中断而从队列中检索第二媒体处理并将第二媒体处理命令发送到第二媒体单元。 响应于接收到来自第一媒体单元的中断，电路可以将数据从第一媒体单元复制到第二媒体单元。

公开(公告)号：WO2016053490A1

公开(公告)日：2016-04-07

申请号：PCT/US2015/045585

申请日：2015-08-17

Applicant: APPLE INC.

Inventor： DE LA CROPTE DE CHANTERAC, Cyril ,  GULATI, Manu ,  MACHNICKI, Erik P. ,  COX, Keith ,  MILLET, Timothy J.

IPC: G06F1/32

CPC classification number: G06F1/3234 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D10/172

Abstract: Embodiments of a method that allow the adjustment of performance settings of a computing system are disclosed. One or more functional units may include multiple monitor circuits, each of which may be configured to monitor a given operational parameter of a corresponding functional unit. Upon detection of an event related to a monitored operational parameter, a monitor circuit may generate an interrupt. In response to the interrupt a processor may adjust one or more performance settings of the computing system.

Abstract translation: 公开了允许调整计算系统的性能设置的方法的实施例。 一个或多个功能单元可以包括多个监视器电路，每个监视器电路可以被配置为监视对应功能单元的给定操作参数。 在检测到与所监视的操作参数有关的事件时，监视器电路可产生中断。 响应于中断，处理器可以调整计算系统的一个或多个性能设置。

公开(公告)号：WO2012096835A1

公开(公告)日：2012-07-19

申请号：PCT/US2012/020440

申请日：2012-01-06

Applicant: APPLE INC. ,  MACHNICKI, Erik P. ,  MILLET, Timothy J. ,  DE CESARE, Josh P.

Inventor： MACHNICKI, Erik P. ,  MILLET, Timothy J. ,  DE CESARE, Josh P.

IPC: G01K1/08

CPC classification number: G06F1/3203 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D10/172

Abstract: Systems and methods for coordinating performance parameters in multiple domains are described. In an embodiment, a method includes receiving a request to change a state of an electronic circuit, where the circuit includes a first domain and a second domain, causing a first parameter of a first circuit serving the first domain to be modified to a first modified parameter based on the request, and causing a second parameter of a second circuit serving the second domain to be modified to a second modified parameter based on the request. In some cases, a parameter may include a clock frequency. In other cases, a parameter may include a voltage. In some embodiments, a system may be implemented as a logic circuit and/or as a system-on-a-chip (SoC). Devices suitable for using these systems include, for example, desktop and laptop computers, tablets, network appliances, mobile phones, personal digital assistants, e-book readers, televisions, and game consoles.

Abstract translation: 描述用于协调多个域中的性能参数的系统和方法。 在一个实施例中，一种方法包括接收改变电子电路的状态的请求，其中电路包括第一域和第二域，使得服务于第一域的第一电路的第一参数被修改为第一修改 参数，并且基于该请求，使服务于第二域的第二电路的第二参数被修改为第二修改参数。 在某些情况下，参数可以包括时钟频率。 在其他情况下，参数可以包括电压。 在一些实施例中，系统可以被实现为逻辑电路和/或作为片上系统（SoC）。 适用于这些系统的设备包括例如台式和膝上型计算机，平板电脑，网络设备，移动电话，个人数字助理，电子书阅读器，电视机和游戏机。

公开(公告)号：WO2011006096A2

公开(公告)日：2011-01-13

申请号：PCT/US2010/041570

申请日：2010-07-09

Applicant: APPLE INC. ,  WANG, James ,  CHEN, Zongjian ,  KELLER, James B. ,  MILLET, Timothy J.

Inventor： WANG, James ,  CHEN, Zongjian ,  KELLER, James B. ,  MILLET, Timothy J.

IPC: G06F12/08

CPC classification number: G06F12/0802 ,  G06F12/0223 ,  G06F12/08 ,  G06F2212/2515 ,  Y02D10/13

Abstract: In an embodiment, a non-transparent memory unit is provided which includes a non-transparent memory and a control circuit. The control circuit may manage the non-transparent memory as a set of non-transparent memory blocks. Software executing on one or more processors may request a non-transparent memory block in which to process data. The control circuit may allocate a first block, and may return an address (or other indication) of the allocated block so that the software can access the block. The control circuit may also provide automatic data movement between the non-transparent memory and a main memory system to which the non-transparent memory unit is coupled. For example, the automatic data movement may include filling data from the main memory system to the allocated block, or flushing the data in the allocated block to the main memory system after the processing of the allocated block is complete.

Abstract translation: 在一个实施例中，提供了一种非透明存储器单元，其包括非透明存储器和控制电路。 控制电路可以将非透明存储器作为一组非透明存储块来管理。 在一个或多个处理器上执行的软件可以请求处理数据的非透明存储器块。 控制电路可以分配第一块，并且可以返回分配块的地址（或其他指示），使得软件可以访问该块。 控制电路还可以提供非透明存储器与非透明存储器单元耦合到的主存储器系统之间的自动数据移动。 例如，自动数据移动可以包括将数据从主存储器系统填充到分配的块，或者在分配的块的处理完成之后将分配的块中的数据清除到主存储器系统。