公开(公告)号：WO2014052273A1

公开(公告)日：2014-04-03

申请号：PCT/US2013/061316

申请日：2013-09-24

Applicant: APPLE INC.

Inventor： ZHAO, Jie-Hua ,  YANG, Yizhang ,  ZHAI, Jun ,  CHUNG, Chih-Ming

IPC: H01L25/10 ,  H01L25/00

CPC classification number: H01L25/50 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/37001 ,  Y02P80/30 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A PoP (package-on-package) package includes a bottom package coupled to a top package. Terminals on the top of the bottom package are coupled to terminals on the bottom of the top package with an electrically insulating material located between the upper surface of the bottom package and the lower surface of the top package. The bottom package and the top package are coupled during a process that applies force to bring the packages together while heating the packages.

Abstract translation: PoP（封装封装）封装包括一个耦合到顶部封装的底部封装。 底部封装顶部的端子通过位于底部封装的上表面和顶部封装的下表面之间的电绝缘材料耦合到顶部封装的底部上的端子。 底部包装和顶部包装在加工包装的过程中被联接，该过程中施加力以使包装在一起。

公开(公告)号：WO2023034684A1

公开(公告)日：2023-03-09

申请号：PCT/US2022/074965

申请日：2022-08-15

Applicant: APPLE INC.

Inventor： CHEN, Wei ,  ZHAO, Jie-Hua ,  ZHAI, Jun

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/498 ,  H01L23/053 ,  H01L23/00

Abstract: Modules and methods of assembly are described. A module includes a lid mounted on a module substrate and covering a component. A stiffener structure may optionally be mounted between the lid and module substrate. A recess can be formed in any of an outer wall bottom surface of the lid, and top or bottom surface of the stiffener structure such that an adhesive layer at least partially fills the recess.

公开(公告)号：WO2020176313A1

公开(公告)日：2020-09-03

申请号：PCT/US2020/018883

申请日：2020-02-19

Applicant: APPLE INC.

Inventor： ZHONG, Chonghua ,  ZHAI, Jun ,  HU, Kunzhong

IPC: H01L23/538

Abstract: Package structure with folded die arrangements and methods of fabrication are described. In an embodiment, a package structure includes a first die and vertical interposer side-by-side. A second die is face down on an electrically connected with the vertical interposer, and a local interposer electrically connects the first die with the vertical interposer.

公开(公告)号：WO2018226394A3

公开(公告)日：2018-12-13

申请号：PCT/US2018/033813

申请日：2018-05-22

Applicant: APPLE INC.

Inventor： ZHAI, Jun ,  ZHONG, Chonghua ,  HU, Kunzhong

IPC: H01L21/60 ,  H01L23/16 ,  H01L23/498 ,  H01L21/48 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H01L21/98 ,  H01L21/683 ,  H01L25/18

Abstract: Multiple component package structures are described in which an interposer chiplet (110) is integrated to provide fine routing between components. In an embodiment, the interposer chiplet (110) and a plurality of conductive vias (142) are encapsulated in an encapsulation layer (140). A first plurality of terminals (135A) of the first (130) and second (132) components may be in electrical connection with the plurality of conductive pillars and a second plurality of terminals (135B) of first and second components may be in electrical connection with the interposer chiplet (110).

公开(公告)号：WO2016010859A1

公开(公告)日：2016-01-21

申请号：PCT/US2015/040013

申请日：2015-07-10

Applicant: APPLE INC.

Inventor： ZHAI, Jun ,  HU, Kunzhong ,  ZHONG, Chonghua

IPC: H01L25/10 ,  G11C5/02 ,  H01L25/18

CPC classification number: H01L25/105 ,  H01L23/49811 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/014 ,  H01L2924/00

Abstract: In some embodiments, a semiconductor device package on package assembly may include a first package, a second package, and a third package. The first package may include a first surface, a second surface, a first die, and a first set of electrical conductors. The first set of electrical conductors may be configured to electrically connect the package on package assembly. The second package may include a third surface and a fourth surface, and a local memory module. The third surface may be coupled to the second surface. The first package may be electrically coupled to the second package. The third package may include a fifth surface and a sixth surface, and a main memory module. The fifth surface may be coupled to the fourth surface. The third package may be electrically coupled to the first package and/or the second package.

Abstract translation: 在一些实施例中，封装组件上的半导体器件封装可以包括第一封装，第二封装和第三封装。 第一封装可以包括第一表面，第二表面，第一管芯和第一组电导体。 第一组电导体可以被配置为电连接封装组件上的封装。 第二包装可以包括第三表面和第四表面以及本地存储器模块。 第三表面可以联接到第二表面。 第一封装可以电耦合到第二封装。 第三包装可以包括第五表面和第六表面，以及主存储器模块。 第五表面可以联接到第四表面。 第三封装可以电耦合到第一封装和/或第二封装。

公开(公告)号：WO2015199817A1

公开(公告)日：2015-12-30

申请号：PCT/US2015/029218

申请日：2015-05-05

Applicant: APPLE INC.

Inventor： PANG, Mengzhi ,  ZHAI, Jun

IPC: H01L23/538 ,  H01L21/60 ,  H01L25/10 ,  H01L21/56

CPC classification number: H01L25/18 ,  H01L21/56 ,  H01L21/568 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/24195 ,  H01L2224/73209 ,  H01L2224/81005 ,  H01L2224/92124 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2224/81

Abstract: A semiconductor device package includes a logic die (102) coupled to a memory die (108) in a face-to-face configuration with small interconnect pitch (at most about 50 pm) and small distances between the die (at most about 50 pm). The logic die may be connected to a redistribution layer (112) with terminals that are fanned out, or spaced out, to provide space for the face-to-face connections to the memory die. The memory die may be connected to the logic die before or after the logic die is connected to the redistribution layer. The logic die and the memory die may be at least partially encapsulated in an encapsulant (110). Routing (114) in the redistribution layer may connect the logic die and/or the memory die to ball grid array terminals coupled to the bottom of the redistribution layer and/or discrete devices (118) coupled to the redistribution layer.

Abstract translation: 半导体器件封装包括以小的互连间距（至多约50μm）和裸片之间的距离小（至多约50μm）以面对面配置耦合到存储器管芯（108）的逻辑管芯（102） ）。 逻辑管芯可以连接到再分配层（112），端子被扇形出或间隔开，以提供用于与存储管芯的面对面连接的空间。 在逻辑管芯连接到再分配层之前或之后，存储器管芯可以连接到逻辑管芯。 逻辑管芯和存储管芯可以至少部分地封装在密封剂（110）中。 再分配层中的路由（114）可以将逻辑管芯和/或存储管芯连接到耦合到再分配层的底部的球栅阵列端子和/或耦合到再分配层的分立器件（118）。

公开(公告)号：WO2014120483A1

公开(公告)日：2014-08-07

申请号：PCT/US2014/012050

申请日：2014-01-17

Applicant: APPLE INC.

Inventor： ZHAI, Jun

IPC: H01L25/10 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/3128 ,  H01L23/145 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L25/105 ,  H01L2224/12105 ,  H01L2224/13124 ,  H01L2224/136 ,  H01L2224/13611 ,  H01L2224/24101 ,  H01L2224/24227 ,  H01L2224/244 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/821 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/00

Abstract: A PoP (package-on-package) package includes a bottom package (120) coupled to a top package (100). The bottom package includes a die (108) coupled to an interposer layer (102) with an adhesive layer (110). One or more terminals (104) are coupled to the interposer layer on the periphery of the die. The terminals and the die are at least partially encapsulated in an encapsulant (112). The terminals and the die are coupled to a redistribution layer (RDL). Terminals (116) on the bottom of the RDL (114) are used to couple the PoP package to a motherboard or a printed circuit board (PCB). One or more additional terminals (132) couple the interposer layer to the top package. The additional terminals may be located anywhere along the surface of the interposer layer.

Abstract translation: PoP（封装封装）封装包括耦合到顶部封装（100）的底部封装（120）。 底部包装包括与粘合剂层（110）连接到插入层（102）的管芯（108）。 一个或多个端子（104）耦合到管芯外围上的插入层。 端子和管芯至少部分地封装在密封剂（112）中。 端子和管芯耦合到再分配层（RDL）。 RDL（114）底部的端子（116）用于将PoP封装耦合到主板或印刷电路板（PCB）。 一个或多个附加端子（132）将插入层耦合到顶部封装。 附加端子可以位于沿着插入层的表面的任何位置。