公开(公告)号：CA2028551A1

公开(公告)日：1991-05-04

申请号：CA2028551

申请日：1990-10-25

Applicant: COMPAQ COMPUTER CORP

Inventor： THAYER JOHN S ,  MAYER DALE J ,  IZQUIERDO JAVIER F ,  CULLEY PAUL R ,  LANDRY JOHN A

IPC: G06F12/06 ,  G06F12/00

Abstract: DATA DESTINATION FACILITY A memory mapping and module enabling circuit for allowing logical 128 kbyte memory blocks to be defined for any location in any module connected to a memory system. A RAM is addressed by the system address lines defining 128 kbyte blocks, with the output data providing the row address strobe enable signals for a particular memory module and the address values necessary to place the 128 kbyte block within the module. Various other parameters such as write protect status and memory location are also provided by the RAM. Circuits and techniques for programming and reading the RAM are provided.

公开(公告)号：JPH10233797A

公开(公告)日：1998-09-02

申请号：JP36069797

申请日：1997-12-26

Applicant: COMPAQ COMPUTER CORP

Inventor： HARESKI PATRICIA E ,  WALKER WILLIAM J ,  KOTZUR GARY B ,  MAYER DALE J ,  WITKOWSKI MICHAEL L

IPC: G06F13/00 ,  H04L12/24 ,  H04L12/56 ,  H04L12/46 ,  H04L12/28 ,  H04L12/66

Abstract: PROBLEM TO BE SOLVED: To collect statistical information by an efficient method without forcing a processor to be in multiple standby states by connecting the processor to a processor bus, asserting a statistics request signal, receiving a statistics response signal and retrieving statistical information from a memory. SOLUTION: A CPU 230 as the processor initializes a TPI 220 and an EPSM 210 and executes the processing of configuration with the power-up of a network switch 102. The CPU 230 monitors and collects statistical information. The CPU 230 announces the statistics request signal and detects the assertion of the statistics response signal. Statistical information from the memory 212 is retrieved at the same time as the detection of the response signal. While information is collected by a switch manager, the other tasks are freely completed. Thus, the efficiency of the CPU 230 and the network switch 102 is increased.

公开(公告)号：JPH10232851A

公开(公告)日：1998-09-02

申请号：JP36145797

申请日：1997-12-26

Applicant: COMPAQ COMPUTER CORP

Inventor： KOTZUR GARY B ,  HARESKI PATRICIA E ,  WITKOWSKI MICHAEL L ,  MAYER DALE J ,  WALKER WILLIAM J

IPC: G06F15/16 ,  G06F13/362 ,  G06F15/17 ,  G06F15/177 ,  H04L12/56 ,  G06F15/173

Abstract: PROBLEM TO BE SOLVED: To determine priority for selecting any port and performing any service by monitoring ports and programming the priority in a memory based on a priority scheme selected by a control logic. SOLUTION: Respective ports 104 and 110 include reception priority count and transmission priority count and they are assigned according to the selected mediation scheme. Concerning round robbin priority and weight priority, the reception priority count and the transmission priority count are loaded from a weight factor. When the ports 104 and 110 request services, a monitor logic updates active values corresponding to these ports. Then, the monitor logic is connected to a memory 212 and the control logic, monitors the respective ports 104 and 110 and programs the priority in the memory 212 according to the priority scheme selected by the control logic.

公开(公告)号：JPH10215282A

公开(公告)日：1998-08-11

申请号：JP36127697

申请日：1997-12-26

Applicant: COMPAQ COMPUTER CORP

Inventor： MAYER DALE J ,  RICHTER ROGER ,  WITKOWSKI MICHAEL L ,  KOTZUR GARY B ,  HARESKI PATRICIA E ,  WALKER WILLIAM J

IPC: G06F13/00 ,  H04L12/56 ,  H04L12/28 ,  H04L12/46

Abstract: PROBLEM TO BE SOLVED: To provide the network switch that attains communication among network devices. SOLUTION: Upon the receipt of data from a network device 106, the network switch 102 stores device identification information to identify the network device, a port number, control information and packet data. The switch includes a switch manager that controls a data flow between a port and a central memory. Each identification entry is arranged in a central memory of a hash address obtained by hashing a definite network address. A hash logic of the switch manager receives each network address to decide the hash address used to access the identification entry and hashes it. The memory is configured to take a chain structure to access an entry quickly.

公开(公告)号：JPH10215275A

公开(公告)日：1998-08-11

申请号：JP29198

申请日：1998-01-05

Applicant: COMPAQ COMPUTER CORP

Inventor： WALKER WILLIAM J ,  KOTZUR GARY B ,  HARESKI PATRICIA E ,  MAYER DALE J ,  WITKOWSKI MICHAEL L

IPC: G06F13/00 ,  H04L12/56 ,  H04L12/46 ,  H04L12/28 ,  H04L12/66

Abstract: PROBLEM TO BE SOLVED: To obtain a network overhead function by a network switch which has one or more network ports each including a network interface, a data path interface, and a processor port interface. SOLUTION: A CPU 230 initializes TPI 220 and FPSM 210 and performs a processing for configuration once powered up with a network switch 102. Statistical information is monitored and gathered and functions of various devices of the network switch 102 are managed and controlled in operation. The CPU 230 functions as an additional network port and is coupled with EPSM 210 through an address and data part 218a and a CPU bus 218 including a relative control and state signal 218b. Thus, the CPU 230 has the overhead function, and consequently the bandwidth for data transfer of a data bus increases.