公开(公告)号：CA2026771A1

公开(公告)日：1991-05-04

申请号：CA2026771

申请日：1990-10-02

Applicant: COMPAQ COMPUTER CORP

Inventor： IZQUIERDO JAVIER F ,  LANDRY JOHN A

IPC: G06F12/02 ,  G06F12/08 ,  G06F15/17 ,  G06F13/14 ,  G06F9/46

Abstract: A method for communication between multiple processors using registers that are accessed by four register select lines which are translated from the original system address. The address translation is performed off of the main processor board to reduce loading effects on the local bus and reduces the pin count of processor board. A signal representing which of the processors is currently active is used as a pseudo address line for the purpose of the translation. The original addresses of the I/O registers may be either input/output or memory mapped.

公开(公告)号：CA2027799A1

公开(公告)日：1991-05-04

申请号：CA2027799

申请日：1990-10-17

Applicant: COMPAQ COMPUTER CORP

Inventor： MILLER DAVID A ,  JANSEN KENNETH A ,  CULLEY PAUL R ,  TAYLOR MARK E ,  IZQUIERDO JAVIER F

IPC: G06F1/24 ,  G06F12/08 ,  G06F15/177 ,  G06F9/22 ,  G06F9/30

Abstract: A method and system for independently resetting primary and secondary processors 20 and 120 respectively under program control in a multiprocessor, cache memory system. Processors 20 and 120 are reset without causing cache memory controllers 24 and 124 to reset.

公开(公告)号：CA2028551A1

公开(公告)日：1991-05-04

申请号：CA2028551

申请日：1990-10-25

Applicant: COMPAQ COMPUTER CORP

Inventor： THAYER JOHN S ,  MAYER DALE J ,  IZQUIERDO JAVIER F ,  CULLEY PAUL R ,  LANDRY JOHN A

IPC: G06F12/06 ,  G06F12/00

Abstract: DATA DESTINATION FACILITY A memory mapping and module enabling circuit for allowing logical 128 kbyte memory blocks to be defined for any location in any module connected to a memory system. A RAM is addressed by the system address lines defining 128 kbyte blocks, with the output data providing the row address strobe enable signals for a particular memory module and the address values necessary to place the 128 kbyte block within the module. Various other parameters such as write protect status and memory location are also provided by the RAM. Circuits and techniques for programming and reading the RAM are provided.