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    ASSOCIATIVE MAP WITH LEAST RECENTLY USED (LRU) REPLACEMENT
    32.
    发明专利
    ASSOCIATIVE MAP WITH LEAST RECENTLY USED (LRU) REPLACEMENT 未知

    公开(公告)号：CA2021272C

    公开(公告)日：1994-03-29

    申请号：CA2021272

    申请日：1990-07-16

    Applicant: IBM

    Inventor： BEAUSOLEIL WILLIAM F ,  NG TAK-KWONG

    IPC: G06F12/10 ,  G06F12/12 ,  G06F7/02

    Abstract: A least recently used associative map is described for translating virtual memory addresses to real memory addresses. The map includes a stack of storage devices each with a comparator. The storage devices are arranged in a push down stack with an input storage device to receive the incoming virtual address and store the corresponding real address and the other storage devices coupled to the output of the previous higher storage devices and with storage devices storing the translation of virtual address and real address in order of recent use with the last or bottom storage device storing the least recently used address. When the comparator detects a compare that real address is provided out and that translation is applied to the input storage device as the most recently used translation and the other translations are shifted down the stack to replace in the storage device that had the compare with the translation from the previous storage device. If there is not a compare a new translation is entered at the input storage device and the other translations are shifted down with the least recently used being shifted out if the storage devices are full.

    ARRAY LOGIC SYSTEMS FOR USE IN PATTERN RECOGNITION EQUIPMENTS AND THE LIKE
    33.
    发明专利
    ARRAY LOGIC SYSTEMS FOR USE IN PATTERN RECOGNITION EQUIPMENTS AND THE LIKE 未知

    公开(公告)号：CA1049145A

    公开(公告)日：1979-02-20

    申请号：CA225120

    申请日：1975-04-17

    Applicant: IBM

    Inventor： BEAUSOLEIL WILLIAM F ,  HILLER RICHARD

    IPC: G06K9/03 ,  G06K9/46 ,  H03K19/177 ,  G06K9/06 ,  H03K19/08

    Abstract: A fabrication arrangement using plural LSI chips to make a bit stream detection system requiring a programmable logic array which is too large to fit on a single LSI chip. Due to the small number of input/output pins available on any LSI chip, the fabrication arrangement divides among the chips an input shift register, the array, and array input latches. Each LSI chip also has time-multiplexed array outputs and time-multiplexed feedback inputs that minimize the pins and enable interconnection among the array section outputs on the chips so that they combine into the single large array required by the detection system. These LSI chips can be identically fabricated.

    34.
    发明专利
    未知

    公开(公告)号：FR2276738A1

    公开(公告)日：1976-01-23

    申请号：FR7515093

    申请日：1975-05-06

    Applicant: IBM

    Inventor： BEAUSOLEIL WILLIAM F ,  HILLER RICHARD ,  OTTAWAY GERALD H ,  WINKLER VAUGHN D

    IPC: G06F7/48 ,  G06K9/46 ,  H03K19/173 ,  H03K19/177 ,  H03K19/20 ,  G06K9/00 ,  G11C19/14

    Abstract: 1476880 Character recognition programmable logic circuit INTERNATIONAL BUSINESS MACHINES CORP 17 April 1975 [24 June 1974 (2)] 15770/75 Heading G4R A logic circuit arrangement for use in a character recognition device has a shift register SR1- 48 feeding a plurality of programmable logic circuits P AND 1-48. Data representing for instance a scanning matric 40 Î 24 is fed serially to a 960 bit shift register formed of 48 20 bit sections. Each section feeds a plurality of programmable AND circuits 1-48 each of which produces a one bit output which is fed back to 64 feedback latches which also feed the P AND circuits. Selected P AND circuits 37-48 also feed output latches. The P AND circuits may be as shown in Fig. 8C for a three input gate in which latches 115, 116, 124, 125, 133, 134 are set to determine the logic operation. If both latches for an input are zero the inverters, e.g. 119, 120 for input A feed "1"s to AND gate 123. If only one is zero then either A or A is fed to gate 123. OR functions are produced using inverters and de Morgan's theorem A - B = A + B. The shift register may contain dummy registers which are not connected to the logic circuits to reduce the number of connections required while still storing the same number of bits. Thus portions of an area are processed alternately (Fig. 14, not shown).

    MONOLITHIC MEMORY UTILIZING DEFECTIVE STORAGE CELLS
    35.
    发明专利
    MONOLITHIC MEMORY UTILIZING DEFECTIVE STORAGE CELLS 未知

    公开(公告)号：CA954218A

    公开(公告)日：1974-09-03

    申请号：CA122496

    申请日：1971-09-10

    Applicant: IBM

    Inventor： BEAUSOLEIL WILLIAM F

    IPC: G11C11/413 ,  G06F12/16 ,  G11C8/00 ,  G11C29/00 ,  G11C29/04

    Abstract: 1311221 Digital data storage INTERNATICNAL BUSINESS MACHINES CORP 19 May 1971 [30 Sept 1970] 15759/71 Heading G4C A store comprises a number of units each containing a plurality of bit cells, corresponding cells from each unit storing a word, and the units are arranged so that bit cells which are known to be defective are situated in corresponding notional areas of the units, these areas being excluded from the addresses supplied by a system-store address translator. A memory may be made up from circuit cards each of which carries a plurality of modules, each module comprising four chips and each chip being divided into four notional quadrants. In manufacture, chips which are known to have defective cells in the same one, two or three quadrants are placed in the same chip position on the modules to form full-, half-, quarter- or three-quarter-size memories. For example, two ¢-size and four ¥-size memories may be combined to form a memory having a usable capacity four times that of a single perfect memory, the addressing circuitry being arranged to address non-defective words in a contiguous sequence of addresses, defective words occupying addresses notionally higher than the sequence.

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