公开(公告)号：AU3180084A

公开(公告)日：1985-02-14

申请号：AU3180084

申请日：1984-08-10

Applicant: IBM

Inventor： KUMMER DAVID ALLEN ,  RACKLEY DARWIN PRESTON ,  SAENZ JESUS ANDRES

IPC: G09G1/06 ,  G09G1/16 ,  G09G5/00 ,  G09G5/40 ,  G06F3/153

Abstract: @ A raster scan display system includes a plurality of storage maps (MAPO to MAP4). These maps are addressable in either of two modes. In the first mode each map contains bit mapped data and the maps are addressed together to provide colour signals from which colour video signals are derived. In the second mode, one map contains character representing data and a further map, character display dot patterns. In this mode the first map is addressed to provide partial addresses for the further map. These partial addresses are combined with row scan data signals to access the further map from which the character display dot data is used to generate the video signals.

公开(公告)号：AT57028T

公开(公告)日：1990-10-15

申请号：AT84107805

申请日：1984-07-05

Applicant: IBM

Inventor： KUMMER DAVID ALLEN

IPC: G06F12/02 ,  G06F3/153 ,  G06F12/06 ,  G06F13/16

Abstract: In a microcomputer system having a main memory accessed by both a central processor unit (20) and a CRT controller (21), a page register system (30) receives page bits defining both CPU and CRT pages from CPU. The CPU page bits are combined with lower order address bits from CPU for CPU access cycles, and CRT page bits are combined with lower order address bits from CRT controller for CRT access cycles. Both CPU and CRT controller can access any of pages in memory. For compatibility with higher level systems, the CPU may provide addresses in a range outside range of addresses for memory. When a decoder (42) detects such addresses, it directs CPU address bits, corresponding in order to CPU page bits issued by the register system, to address memory.

公开(公告)号：HK18590A

公开(公告)日：1990-03-16

申请号：HK18590

申请日：1990-03-08

Applicant: IBM

Inventor： EGGEBRECHT LEWIS CLARK ,  KUMMER DAVID ALLEN

IPC: G06F12/06

Abstract: PCT No. PCT/US81/01078 Sec. 371 Date Mar. 31, 1983 Sec. 102(e) Date Mar. 31, 1983 PCT Filed Aug. 12, 1981 PCT Pub. No. WO83/00576 PCT Pub. Date Feb. 17, 1983.A computing system storage addressing apparatus which extends the addressing capability of an address bus to enable direct storage (memory) storage access (DMA) channels to operate simultaneously in the same or different storage page. The computing system includes a processor, a plurality of storage devices, a data bus and an address bus interconnecting the processor and the storage devices, a DMA device controlling connection of a plurality of DMA channels to the address bus and data bus, a plurality of address register means for storing page address signals loaded from the processor, and gating means for gating to the address bus page address signals from an address register means corresponding to a currently active DMA channel.

公开(公告)号：AT49315T

公开(公告)日：1990-01-15

申请号：AT84107799

申请日：1984-07-05

Applicant: IBM

Inventor： KUMMER DAVID ALLEN ,  SAENZ JESUS ANDRES ,  TRYNOSKY STEPHEN WAYNE

IPC: G09G5/00 ,  G06F3/00 ,  G06F3/14 ,  G06F7/02 ,  G06T7/00 ,  G09G1/16 ,  G09G5/02 ,  G09G5/393 ,  G09G5/395 ,  G06F15/70

Abstract: In a bit mapped raster scan digital display system, a number of maps (MAPO-MAP3), each contain a single component of the display data and are read together to provide sets of bytes, each set representing eight pel defining groups. A compare system is provided for determining when a pel group in a set of bytes compares with a reference pel defining group. For the, or each, pair of maps, the compare system compares each bit of the two bytes of data with the correspondingly positioned bit of the reference group to provide outputs when a corresponding bit in each of the bytes compares with the two reference bits. When more than two maps are employed the compare outputs related to all of the pairs of maps are combined to provide an output signal when a pel group in a byte from the maps compares with the reference bits. In a modification of the system, the comparison can be made between one or more of the maps and the corresponding bit or bits of the compare data.

公开(公告)号：MX156485A

公开(公告)日：1988-08-26

申请号：MX20131084

申请日：1984-05-10

Applicant: IBM

Inventor： KUMMER DAVID ALLEN ,  RACKLEY DARWIN PRESTON ,  SAENZ JESUS AMORES

IPC: G09G1/16 ,  G09G1/06 ,  G09G5/00 ,  G09G5/40 ,  G11C13/04

Abstract: @ A raster scan display system includes a plurality of storage maps (MAPO to MAP4). These maps are addressable in either of two modes. In the first mode each map contains bit mapped data and the maps are addressed together to provide colour signals from which colour video signals are derived. In the second mode, one map contains character representing data and a further map, character display dot patterns. In this mode the first map is addressed to provide partial addresses for the further map. These partial addresses are combined with row scan data signals to access the further map from which the character display dot data is used to generate the video signals.

公开(公告)号：DE3278546D1

公开(公告)日：1988-06-30

申请号：DE3278546

申请日：1982-07-23

Applicant: IBM

Inventor： SAENZ JESUS ANDRES ,  DEAN MARK EDWARD ,  KUMMER DAVID ALLEN

IPC: G09G5/02 ,  G09G1/28

公开(公告)号：AU569315B2

公开(公告)日：1988-01-28

申请号：AU3180084

申请日：1984-08-10

Applicant: IBM

Inventor： KUMMER DAVID ALLEN ,  RACKLEY DARWIN PRESTON ,  SAENZ JESUS ANDRES

IPC: G09G1/06 ,  G09G1/16 ,  G09G5/00 ,  G09G5/40 ,  G06F3/153

Abstract: @ A raster scan display system includes a plurality of storage maps (MAPO to MAP4). These maps are addressable in either of two modes. In the first mode each map contains bit mapped data and the maps are addressed together to provide colour signals from which colour video signals are derived. In the second mode, one map contains character representing data and a further map, character display dot patterns. In this mode the first map is addressed to provide partial addresses for the further map. These partial addresses are combined with row scan data signals to access the further map from which the character display dot data is used to generate the video signals.

公开(公告)号：MX154653A

公开(公告)日：1987-11-12

申请号：MX20137184

申请日：1984-05-17

Applicant: IBM

Inventor： KUMMER DAVID ALLEN

IPC: G06F3/153 ,  G06F3/12 ,  G06F12/00 ,  G06F12/06 ,  G06F13/00 ,  G06K15/00 ,  H04N9/00 ,  G06F12/08

Abstract: A microcomputer includes a main memory system which is accessed, substantially independently, by the CPU and a subsystem, for example a video display subsystem (12,11). The memory system comprises a base memory (22) and an optional add-ori expansion memory (42). When only the base memory is installed, consecutive locations have consecutively numbered addresses, and both the CPU and subsystem access individual locations. When both memories are installed, one has even numbered addresses and the other odd numbered addresses. With both memories installed, the CPU still accesses individual locations, but the subsystem addresses even addresses to obtain, for each access, data from the even address and the next higher odd address, thereby accessing a location in both memories. Thus the memory bandwith for the subsystem is effectively doubled when the expansion memory is installed.

公开(公告)号：AU566038B2

公开(公告)日：1987-10-08

申请号：AU3137484

申请日：1984-08-01

Applicant: IBM

Inventor： KUMMER DAVID ALLEN ,  SAENZ JESUS ANDRES ,  TRYNOSKY STEPHEN WAYNE

IPC: G09G5/00 ,  G09G5/34 ,  G09G5/395 ,  G06F3/153

Abstract: In a raster scan digital display system, a display image is stored, as coded characters or a bit map, which is larger than the display image. In order to define an image, within the stored image, for display, the addressing system for the memory (or memories) storing the image include a display image defining circuit. This circuit includes an address counter which is incremented to define successive addresses of data in a line of the displayed image, or row of characters therein. The circuit includes a first register to receive the initial address of a display image and a second register to receive a value indicating the width of the stored image. For the initial line (or character row) of a displayed image, the address counter is loaded from the first register and incremented from the initial address. For each subsequent line (or character row) the address from which the counter is incremented is the sum of the initial address of the previous line (or character row) and the value in the second register.

公开(公告)号：AU565702B2

公开(公告)日：1987-09-24

申请号：AU3098884

申请日：1984-07-24

Applicant: IBM

Inventor： KUMMER DAVID ALLEN

IPC: G06F3/12 ,  G06F3/153 ,  G06F12/00 ,  G06F12/06 ,  G06F13/00 ,  G06K15/00 ,  H04N9/00

Abstract: A microcomputer includes a main memory system which is accessed, substantially independently, by the CPU and a subsystem, for example a video display subsystem (12,11). The memory system comprises a base memory (22) and an optional add-ori expansion memory (42). When only the base memory is installed, consecutive locations have consecutively numbered addresses, and both the CPU and subsystem access individual locations. When both memories are installed, one has even numbered addresses and the other odd numbered addresses. With both memories installed, the CPU still accesses individual locations, but the subsystem addresses even addresses to obtain, for each access, data from the even address and the next higher odd address, thereby accessing a location in both memories. Thus the memory bandwith for the subsystem is effectively doubled when the expansion memory is installed.