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    31.
    发明专利
    未知

    公开(公告)号：DE3786125D1

    公开(公告)日：1993-07-15

    申请号：DE3786125

    申请日：1987-06-26

    Applicant: IBM

    Inventor： LUMELSKY LEON

    IPC: G09G5/00 ,  G09G5/06 ,  G09G5/36 ,  G09G5/39 ,  G09G5/391 ,  G09G5/395 ,  G09G1/16

    Abstract: A display controller provides multiple different resolutions by selectively enabling different combinations of shift registers (SHR0-SHR7) between the frame buffer and video look-up tables (VLTs). The VLTs are partitioned, with different partitions being programmed identically in accordance with the values of only the number of address bits which will be active from the shift registers at any one time. For example, reading out any of the 512 lines of the frame buffer twice in succession, before incrementing the line counter to access the next line, allows for using one half of the stored bits each time such line is read, to simulate a horizontal resolution having the double number of pixels. Alternatively, making two consecutive passes through the buffer and using each time a different half of the stored bits, allows for simulating a vertical resolution comprising the double number of display lines.

    PARALLEL RENDERING OF SMOOTHLY SHADED COLOR TRIANGLES WITH ANTI-ALIASED EDGES FOR A THREE DIMENSIONAL COLOR DISPLAY
    34.
    发明专利
    PARALLEL RENDERING OF SMOOTHLY SHADED COLOR TRIANGLES WITH ANTI-ALIASED EDGES FOR A THREE DIMENSIONAL COLOR DISPLAY 未知

    公开(公告)号：CA1309198C

    公开(公告)日：1992-10-20

    申请号：CA577725

    申请日：1988-09-16

    Applicant: IBM

    Inventor： EVANGELISTI CARLO J ,  LUMELSKY LEON ,  PAVICIC MARK J

    IPC: G06T15/50 ,  G06F15/72

    Abstract: YO986-065 PARALLEL RENDERING OF SMOOTHLY SHADED COLOR TRIANGLES WITH ANTI-ALIASED EDGES FOR A THREE DIMENSIONAL COLOR DISPLAY The present invention comprises a method for utilizing an SIMD computer architecture in conjunction with a host processor and coordinate processor to render quality, three-dimensional, anti-aliased shaded color images into the frame buffer of a video display system. The method includes a parallel algorithm for rendering an important graphic primitive for accomplishing the production of a smoothly shaded color three-dimensional triangle with anti-aliased edges. By taking advantage of the SIMD architecture and said parallel algorithm, the very time consuming pixel by pixel computations are broken down for parallel execution. A single coordinate processor computes and transmits an overall triangle record which is essentially the same for all blocks of pixels within a given bounding box which box in turn surrounds each triangle. The individual pixel data is produced by a group of M x N pixel processors and stored in the frame buffer in a series of repetitive steps wherein each step corresponds to the processing of an M x N block of pixels within the bounding box of the triangle. Thus, each pixel processor performs the same operation, modifying its computations in accordance with triangle data received from the coordinate processor and positional data unique to its own sequential connectivity to the frame buffer, thus allowing parallel access to the frame buffer.

    MULTI-SOURCE IMAGE REAL TIME MIXING AND ANTI-ALIASING
    35.
    发明专利
    MULTI-SOURCE IMAGE REAL TIME MIXING AND ANTI-ALIASING 未知

    公开(公告)号：CA2068042C

    公开(公告)日：1999-03-02

    申请号：CA2068042

    申请日：1992-05-05

    Applicant: IBM

    Inventor： LUMELSKY LEON ,  CHOI SUNG M ,  PEEVERS ALAN W ,  PITTAS JOHN L

    IPC: G09G5/06 ,  G06T3/00 ,  G06T11/20 ,  G09G5/14 ,  G09G5/36 ,  G09G5/395 ,  H04N5/265 ,  H04N5/272 ,  H04N5/445 ,  H04N7/015

    Abstract: Method and apparatus for implementing a raster graphic display video data path that provides arbitrary mixing of a plurality of images. The video data path is highly parallelized, and employs parallel devices operating under the control of a set of look-up tables. The look-up tables are loadable from a controller, such as a host workstation. The raster graphic display video data path functions with unlimited screen resolutions, and also enables a variety of different pixel data formats from a potentially large number of different sources. Outputs from several image sources are mixed under the control of the host workstation, with a resultant pixel value being based on (a) a combined translucency coefficient (alpha) of the images, for each image source, and (b) a window identification number assigned by the host workstation. Pixel value conversion to a common predetermined format provides coherency between pixel values generated by a number of different image sources, such as HDTV and graphics servers. A separate frame buffer is allocated for each of the sources.

    38.
    发明专利
    未知

    公开(公告)号：DE69211435D1

    公开(公告)日：1996-07-18

    申请号：DE69211435

    申请日：1992-07-02

    Applicant: IBM

    Inventor： LUMELSKY LEON

    IPC: H04N1/41 ,  G09G5/00 ,  G09G5/02 ,  G09G5/36 ,  G09G5/39 ,  G09G5/06

    Abstract: An image buffer is described for an XxY pixel display, which image buffer stores compressed image pixel data for a plurality of n x m matrices of pixels, each matrix represented by a pair of color codes and MASK having nm bit position, each positions mapping to a pixel in the matrix, a manifested bit value in a MASK bit position defining the color code assigned to a mapped pixel. The image buffer includes serial registers for feeding pixel color code values to a buffer serial output and multiplexers for providing n bit values from the MASK on n of its output lines. Gating circuitry, controlled by bit values on the output lines, are operative to gate either a first set of inputs or a second set of inputs into the shift registers. Control circuitry is provided for feeding a pair of color codes and the MASK bit values to the gating circuits and multiplexers, respectively, and for serially operating the serial shift registers in response to the gating of the inputs from the gating circuits.

    39.
    发明专利
    未知

    公开(公告)号：DE69020279T2

    公开(公告)日：1996-02-08

    申请号：DE69020279

    申请日：1990-08-03

    Applicant: IBM

    Inventor： LUMELSKY LEON ,  PEEVERS ALAN W ,  CHOI SUNG MIN

    IPC: G06F3/153 ,  G09G5/14 ,  G09G5/36 ,  G09G5/39 ,  G09G5/395 ,  G09G1/16

    Abstract: A locking mechanism is incorporated in a high-resolution video display system including a high-resolution monitor, a computer for providing controls signals to said display system and two high-resolution frame buffers, one for storing computer generated graphics images and one for storing video data both of said buffers being operable under control of said computer for reading out data to the monitor. The locking mechanism includes an output lock functionally located between the output of both of the frame buffers and the high-resolution monitor for preventing video data from overwriting graphics data on said monitor screen. An input lock is also provided for preventing static video data stored in predetermined regions of the video frame buffer from being continually overwritten by motion video data being continually supplied to the video frame buffer. The output lock utilizes an extra bit-plane in the video buffer which stores a predetermined lock pattern and utilizes the normal monitor output port of the buffer operating under control of standard frame buffer addressing circuitry in combination with straight-forward combinational logic to achieve the locking function. The input lock utilizes a small DRAM which stores the input lock pattern data and utilizes this data in conjunction with normal write operations in the video buffer to control circuitry to disable the write function in predetermined regions of the video buffer.

    40.
    发明专利
    未知

    公开(公告)号：DE69020279D1

    公开(公告)日：1995-07-27

    申请号：DE69020279

    申请日：1990-08-03

    Applicant: IBM

    Inventor： LUMELSKY LEON ,  PEEVERS ALAN W ,  CHOI SUNG MIN

    IPC: G06F3/153 ,  G09G5/14 ,  G09G5/36 ,  G09G5/39 ,  G09G5/395 ,  G09G1/16

    Abstract: A locking mechanism is incorporated in a high-resolution video display system including a high-resolution monitor, a computer for providing controls signals to said display system and two high-resolution frame buffers, one for storing computer generated graphics images and one for storing video data both of said buffers being operable under control of said computer for reading out data to the monitor. The locking mechanism includes an output lock functionally located between the output of both of the frame buffers and the high-resolution monitor for preventing video data from overwriting graphics data on said monitor screen. An input lock is also provided for preventing static video data stored in predetermined regions of the video frame buffer from being continually overwritten by motion video data being continually supplied to the video frame buffer. The output lock utilizes an extra bit-plane in the video buffer which stores a predetermined lock pattern and utilizes the normal monitor output port of the buffer operating under control of standard frame buffer addressing circuitry in combination with straight-forward combinational logic to achieve the locking function. The input lock utilizes a small DRAM which stores the input lock pattern data and utilizes this data in conjunction with normal write operations in the video buffer to control circuitry to disable the write function in predetermined regions of the video buffer.

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