公开(公告)号：FR2315169A1

公开(公告)日：1977-01-14

申请号：FR7615006

申请日：1976-05-13

Applicant: IBM

Inventor： MAGDO INGRID E ,  MAGDO STEVEN

IPC: H01L29/78 ,  H01L21/331 ,  H01L21/76 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/07 ,  H01L27/12 ,  H01L29/04 ,  H01L29/10 ,  H01L29/73 ,  H01L21/72 ,  H01L27/04

Abstract: A method for fabricating both bipolar as well as complementary MOS field effect transistors, i.e., BI-CMOS transistors in the same semiconductor substrate. The preferred embodiment of the method provides bipolar and CMOS transistors having breakdown voltages (BVceo) in excess of 10 volts and CMOS devices having no latchup problems, with a minimum number of processing steps. The method also contemplates the formation of auxiliary devices such as resistors and Schottky Barrier diodes.

公开(公告)号：DE2608214A1

公开(公告)日：1976-10-07

申请号：DE2608214

申请日：1976-02-28

Applicant: IBM

Inventor： MAGDO INGRID EMESE ,  MAGDO STEVEN

IPC: H01L27/04 ,  H01L21/331 ,  H01L21/822 ,  H01L29/73 ,  H01L29/8605 ,  H01C7/00

Abstract: A semiconductor resistor structure for providing a high value resistance particularly adapted for space charge limited transistor applications, the resistor being fabricated in a semiconductor body having a resistivity in excess of 1 ohm cm., more preferably in semiconductor material that is nearly intrinsic. The resistor has two parallel elongated surface diffused regions in the body of an impurity similar to the background impurity of the body and having a surface concentration sufficient to provide an ohmic contact, the boundaries of said surface diffused regions defined by the interface where the impurity concentration of the diffused region is ten percent more than the impurity concentration of the background impurity of the body. In a preferred embodiment, the surface diffused regions are spaced such that the boundaries intersect with each other, and ohmic contact terminals to each of the diffused regions.

公开(公告)号：DE2515707A1

公开(公告)日：1975-12-11

申请号：DE2515707

申请日：1975-04-10

Applicant: IBM

Inventor： MAGDO STEVEN

IPC: H01L21/761 ,  H01L21/331 ,  H01L27/00 ,  H01L29/73 ,  H01L27/08 ,  H01L29/72

Abstract: A space-charge-limited integrated circuit structure featuring optimized geometry to allow maximum packing density of the transistors in a semiconductor substrate.

公开(公告)号：DE2223754A1

公开(公告)日：1972-12-21

申请号：DE2223754

申请日：1972-05-16

Applicant: IBM

Inventor： EMESE MAGDO INGRID ,  MAGDO STEVEN

IPC: H01L21/762 ,  H01L23/29 ,  H01L23/535 ,  H01L27/00 ,  H01L7/64

公开(公告)号：CA1068011A

公开(公告)日：1979-12-11

申请号：CA250133

申请日：1976-04-13

Applicant: IBM

Inventor： MAGDO INGRID E ,  MAGDO STEVEN ,  NESTORK WILLIAM J

IPC: H01L27/00 ,  H01L21/306 ,  H01L21/3063 ,  H01L21/316 ,  H01L21/76 ,  H01L21/762 ,  H01L23/535 ,  B23P1/00 ,  H01L27/12

Abstract: PROCESS FOR FABRICATING DEVICES HAVING DIELECTRIC ISOLATION AND STRUCTURE. A process for forming complete dielectrically isolated monocrystalline silicon regions on a substrate by depositing a first epitaxial silicon layer embodying an N-type impurity on a low resistivity silicon substrate embodying a P-type impurity, forming annular P-type impurity regions in the first epitaxial layer, depositing the second epitaxial layer embodying an N-type impurity on the first epitaxial layer, forming annular P-type impurity regions in the second epitaxial layer in registry with the annular regions in the first epitaxial layer, converting the silicon substrate and the annular P-type regions in the first and second epitaxial layers into porous silicon material by an anodic treatment carried out in an aqueous solution of hydrofluoric acid, and oxidizing the porous silicon material to form silicon oxide. A semiconductor structure having a backing substrate of silicon oxide with monocrystalline silicon islands embedded therein. A preferred embodiment includes low resistivity regions that extend through the substrate.

公开(公告)号：CA1048659A

公开(公告)日：1979-02-13

申请号：CA247252

申请日：1976-03-02

Applicant: IBM

Inventor： MAGDO INGRID E ,  MAGDO STEVEN

IPC: H01L27/04 ,  H01L21/331 ,  H01L21/822 ,  H01L29/73 ,  H01L29/8605 ,  H01L27/02 ,  H01L29/12

Abstract: SEMICONDUCTOR RESISTOR HAVING HIGH VALUE RESISTANCE A semiconductor resistor structure for providing a high value resistance particularly adapted for space charge limited transistor applications, the resistor being fabricated in a semiconductor body having a resistivity in excess of 1 ohm cm., more preferably in semiconductor material that is nearly intrinsic. The resistor has two parallel elongated surface diffused regions in the body of an impurity similar to the background impurity of the body and having a surface concentration sufficient to provide an ohmic contact, the boundaries of said surface diffused regions defined by the interface where the impurity concentration of the diffused region is ten percent more than the impurity concentration of the background impurity of the body. In a preferred embodiment, the surface diffused regions are spaced such that the boundaries intersect with each other, and ohmic contact terminals to each of the diffused regions.

公开(公告)号：CA1039839A

公开(公告)日：1978-10-03

申请号：CA225124

申请日：1975-04-17

Applicant: IBM

Inventor： MAGDO STEVEN

IPC: H01L31/10 ,  H01L27/144 ,  H01L27/146 ,  H01L31/00 ,  H01L27/14

Abstract: SPACE-CHARGE-LIMITED PHOTOTRANSISTOR A space-charge-limited (SCL) transistor is utilized as a phototransistor. The preferred embodiments feature a base diffusion which is shallower than the standard SCL structure and a base geometry for increased light collection while maintaining the high current gain characteristic of SCL transistors.

公开(公告)号：CA1027256A

公开(公告)日：1978-02-28

申请号：CA225329

申请日：1975-04-18

Applicant: IBM

Inventor： MAGDO STEVEN

IPC: H01L21/761 ,  H01L21/331 ,  H01L27/00 ,  H01L29/73

Abstract: A space-charge-limited integrated circuit structure featuring optimized geometry to allow maximum packing density of the transistors in a semiconductor substrate.

公开(公告)号：FR2308201A1

公开(公告)日：1976-11-12

申请号：FR7605145

申请日：1976-02-17

Applicant: IBM

Inventor： MAGDO INGRID E ,  MAGDO STEVEN

IPC: H01L21/033 ,  H01L21/223 ,  H01L21/314 ,  H01L21/76 ,  H01L21/32 ,  H01L21/762 ,  H01L21/318 ,  H01L21/82 ,  H01L27/06

Abstract: In the fabrication of integrated circuits, a method is provided for forming masking structures comprising silicon nitride which avoids the stresses and dislocations associated with direct silicon nitride masking as well as the "bird's beak" problems associated with silicon dioxide-silicon nitride composite mask structures. The mask is formed by first forming a silicon dioxide mask having at least one opening through which the substrate is exposed. Then, a mask comprising silicon nitride is formed on the first mask; this mask has at least one opening laterally smaller than the openings in the first mask and respectively in registration with at least some of the openings in said first mask. Thus, the second mask contacts and covers a portion of the exposed silicon substrate under each of the registered openings.

公开(公告)号：AU8067775A

公开(公告)日：1976-11-04

申请号：AU8067775

申请日：1975-04-30

Applicant: IBM

Inventor： MAGDO STEVEN

IPC: H01L21/761 ,  H01L21/331 ,  H01L27/00 ,  H01L29/73 ,  H01L11/06 ,  H01L5/00 ,  H01L19/00

Abstract: A space-charge-limited integrated circuit structure featuring optimized geometry to allow maximum packing density of the transistors in a semiconductor substrate.