公开(公告)号：US2993999A

公开(公告)日：1961-07-25

申请号：US84988559

申请日：1959-10-30

Applicant: IBM

Inventor： CASMIR KAY ,  MCMURTRIE JOHN S ,  NESTORK WILLIAM J ,  STURTEVANT VERNON O

公开(公告)号：US3922707A

公开(公告)日：1975-11-25

申请号：US47787174

申请日：1974-06-10

Applicant: IBM

Inventor： FREED LARRY E ,  NESTORK WILLIAM J ,  TUMAN DANIEL

IPC: G01R31/28 ,  H01L23/544 ,  H01L27/07 ,  H01L27/04

CPC classification number: H01L22/34 ,  G01R31/2884 ,  H01L27/0755 ,  Y10S148/02 ,  Y10S148/037 ,  Y10S148/053 ,  Y10S148/085 ,  Y10S148/136

Abstract: In integrated semiconductor circuits comprising a plurality of active and passive devices interconnected by conductive means into a selected circuit configuration, the improvement wherein said circuit configuration is arranged so as to be free of possible paths displaying reactance which would be alternative to selected substantially reactanceless paths terminating in critical circuit nodes in the event of structural failure of one of said reactanceless paths, whereby the DC testing of the integrated circuit is not affected by such alternative paths.

Abstract translation: 在包括通过导电装置互连成选定电路配置的多个有源和无源器件的集成半导体电路中，改进之处在于，其中所述电路配置被布置为没有显示电抗的可能路径，该电抗将替代所选择的基本上无电阻的路径 在所述无电阻通路中的一个结构故障的情况下在关键电路节点中，由此集成电路的DC测试不受这种替代路径的影响。

公开(公告)号：CA1182582A

公开(公告)日：1985-02-12

申请号：CA404784

申请日：1982-06-09

Applicant: IBM

Inventor： DOUGHERTY WILLIAM E ,  GREER STUART E ,  NESTORK WILLIAM J ,  NORRIS WILLIAM T

IPC: H01L23/52 ,  H01L23/538

Abstract: AN IMPROVED SEMICONDUCTOR CHIP PACKAGE A substrate for packaging semiconductor chips is provided which is structured with conductors having opposite ends terminating in a mounting surface and intermediate portions extending beneath the surface. The ends of the conductors are arranged in repeating patterns longitudinally along the substrate separated by orthogonal strips free of conductor ends to allow for dense surface wiring. The repeating patterns are arranged to allow for chip mounting sites having sufficient spacing to allow for surface wiring. In this way chips in the same and repeat pattern can be connected by personalized surface wiring and preset subsurface conductors.

公开(公告)号：CA2024639C

公开(公告)日：1993-12-21

申请号：CA2024639

申请日：1990-09-05

Applicant: IBM

Inventor： PRICER WILBUR D ,  FAURE THOMAS B ,  MEYERSON BERNARD S ,  NESTORK WILLIAM J ,  TURNBULL JOHN R JR

IPC: H01L21/302 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/334 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/00 ,  H01L27/04 ,  H01L27/06 ,  H01L27/10 ,  H01L27/108 ,  H01L21/461 ,  H01L29/06

Abstract: ULTRA HIGH DENSITY THREE-DIMENSIONAL SEMICONDUCTOR STRUCTURES Three-dimensional semiconductor structures are taught in which various device types are formed from a plurality of planar layers on a substrate. The major process steps include the formation of a plurality of alternating layers of material, including semiconductor and dielectric materials, forming a vertical access hole in the layers, processing the layers selectively to form active or passive semiconductor devices, and filling the access hole with a conductor. The ultimate structure includes a three-dimensional memory array in which entire dynamic memory cells are fabricated in a stacked vertical orientation above support circuitry formed on a planar surface.

公开(公告)号：FR2312172A1

公开(公告)日：1976-12-17

申请号：FR7610362

申请日：1976-04-01

Applicant: IBM

Inventor： NESTORK WILLIAM J ,  PARIS JOHN A

IPC: H01L23/14 ,  H01L23/538 ,  H01L25/065 ,  H05K1/18

Abstract: The substrate is connected to a metal pattern on a supporting substrate. The method involves making holes in a first plane monocrystal substrate (20); and application of a metallised system on this substrate, with contacts ending at the holes. Metal pins are inserted in the holes; and pins with preformed solder rings are provided. The arrangement is then heated until solder melts and flows in the holes with pins, thus connecting pins with the metallising system; A carrier substrate (12) is provided with a metallurgical system whose contact spots are arranged in a platform corresponding to that of holes in the SC substrate. The ends of the pins are connected with the contact spots.

公开(公告)号：FR2308203A1

公开(公告)日：1976-11-12

申请号：FR7605923

申请日：1976-02-25

Applicant: IBM

Inventor： MAGDO INGRID E ,  MAGDO STEVEN ,  NESTORK WILLIAM J

IPC: H01L27/00 ,  H01L21/306 ,  H01L21/3063 ,  H01L21/316 ,  H01L21/76 ,  H01L21/762 ,  H01L23/535

Abstract: A process for forming complete dielectrically isolated monocrystalline silicon regions on a substrate by depositing a first epitaxial silicon layer embodying an N-type impurity on a low resistivity silicon substrate embodying a P-type impurity, forming annular P-type impurity regions in the first epitaxial layer, depositing the second epitaxial layer embodying an N-type impurity on the first epitaxial layer, forming annular P-type impurity regions in the second epitaxial layer in registry with the annular regions in the first epitaxial layer, converting the silicon substrate and the annular P-type regions in the first and second epitaxial layers into porous silicon material by an anodic treatment carried out in an aqueous solution of hydrofluoric acid, and oxidizing the porous silicon material to form silicon oxide.

公开(公告)号：CA1068011A

公开(公告)日：1979-12-11

申请号：CA250133

申请日：1976-04-13

Applicant: IBM

Inventor： MAGDO INGRID E ,  MAGDO STEVEN ,  NESTORK WILLIAM J

IPC: H01L27/00 ,  H01L21/306 ,  H01L21/3063 ,  H01L21/316 ,  H01L21/76 ,  H01L21/762 ,  H01L23/535 ,  B23P1/00 ,  H01L27/12

Abstract: PROCESS FOR FABRICATING DEVICES HAVING DIELECTRIC ISOLATION AND STRUCTURE. A process for forming complete dielectrically isolated monocrystalline silicon regions on a substrate by depositing a first epitaxial silicon layer embodying an N-type impurity on a low resistivity silicon substrate embodying a P-type impurity, forming annular P-type impurity regions in the first epitaxial layer, depositing the second epitaxial layer embodying an N-type impurity on the first epitaxial layer, forming annular P-type impurity regions in the second epitaxial layer in registry with the annular regions in the first epitaxial layer, converting the silicon substrate and the annular P-type regions in the first and second epitaxial layers into porous silicon material by an anodic treatment carried out in an aqueous solution of hydrofluoric acid, and oxidizing the porous silicon material to form silicon oxide. A semiconductor structure having a backing substrate of silicon oxide with monocrystalline silicon islands embedded therein. A preferred embodiment includes low resistivity regions that extend through the substrate.

公开(公告)号：CA997481A

公开(公告)日：1976-09-21

申请号：CA184838

申请日：1973-11-01

Applicant: IBM

Inventor： FREED LARRY E ,  NESTORK WILLIAM J ,  TUMAN DANIEL

IPC: G01R31/28 ,  H01L23/544 ,  H01L27/07

Abstract: In integrated semiconductor circuits comprising a plurality of active and passive devices interconnected by conductive means into a selected circuit configuration, the improvement wherein said circuit configuration is arranged so as to be free of possible paths displaying reactance which would be alternative to selected substantially reactanceless paths terminating in critical circuit nodes in the event of structural failure of one of said reactanceless paths, whereby the DC testing of the integrated circuit is not affected by such alternative paths.