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    31.
    发明专利
    未知

    公开(公告)号：DE602004024254D1

    公开(公告)日：2009-12-31

    申请号：DE602004024254

    申请日：2004-05-06

    Applicant: IBM

    Inventor： HELLER LISA ,  PFEFFER ERWIN ,  PLAMBECK KENNETH ,  SLEGEL TIMOTHY

    IPC: G06F9/30 ,  G06F9/38 ,  G06F12/08 ,  G06F12/10

    Abstract: A method for invalidating translation table entries and clearing corresponding dynamic address translation (DAT) table entries of a translation lookaside buffer (TLB) associated with a processing unit in a computer system, the computer system comprising one or more address translation tables providing translation information to translate virtual addresses to real addresses, wherein address translation table entry information is maintained in the TLB, the method comprising: a) fetching for execution a multifunction Invalidate DAT Table Entry (IDTE) machine instruction, the IDTE instruction comprising an opcode field identifying said instruction and an information field comprising: 1) a first register field for identifying a first register for indicating an origin and type of an address translation table containing a range of one or more entries to be invalidated, 2) a second register field for identifying a second register for including indices used to select a translation table entry in a type of address translation table indicated by the first register, and an option bit for indicating whether a clear by address space control element (ASCE) operation or an invalidating-and-clearing operation is to be performed, and a range field for identifying a number of additional translation table entries, in the address translation table indicated by the first register, to be invalidated, and 3) a third register field for identifying a third register for indicating an origin and type of address translation table to be used when the clear by address space control element operation is to be performed for only selectively clearing TLB entries; and b) executing the fetched IDTE machine instruction, the executing step comprising: i. determining, from the option bit in the second register, whether a clear by address space control element operation is to be performed; ii. responsive to the option bit indicating that the clear by address space control element operation is to be performed, clearing the TLB, independent of the content of the first register, of those entries in which the address translation table origin of a translation table was used to create the entries in the TLB corresponds to the address translation table origin in the third register; iii. responsive to the option bit indicating that the clear by address space control element operation is not to be performed, invalidating the range of address translation table entries of a translation table identified by the range field, and clearing the TLB entries corresponding to the invalidated entries.

    32.
    发明专利
    未知

    公开(公告)号：DK1701269T3

    公开(公告)日：2009-08-03

    申请号：DK06116358

    申请日：2004-05-06

    Applicant: IBM

    Inventor： SLEGEL TIMOTHY ,  HELLER LISA ,  PFEFFER ERWIN ,  PLAMBECK KENNETH

    IPC: G06F12/10 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F12/08

    Abstract: A method for invalidating translation table entries and clearing corresponding dynamic address translation (DAT) table entries of a translation lookaside buffer (TLB) associated with a processing unit in a computer system, the computer system comprising one or more address translation tables providing translation information to translate virtual addresses to real addresses, wherein address translation table entry information is maintained in the TLB, the method comprising: a) fetching for execution a multifunction Invalidate DAT Table Entry (IDTE) machine instruction, the IDTE instruction comprising an opcode field identifying said instruction and an information field comprising: 1) a first register field for identifying a first register for indicating an origin and type of an address translation table containing a range of one or more entries to be invalidated, 2) a second register field for identifying a second register for including indices used to select a translation table entry in a type of address translation table indicated by the first register, and an option bit for indicating whether a clear by address space control element (ASCE) operation or an invalidating-and-clearing operation is to be performed, and a range field for identifying a number of additional translation table entries, in the address translation table indicated by the first register, to be invalidated, and 3) a third register field for identifying a third register for indicating an origin and type of address translation table to be used when the clear by address space control element operation is to be performed for only selectively clearing TLB entries; and b) executing the fetched IDTE machine instruction, the executing step comprising: i. determining, from the option bit in the second register, whether a clear by address space control element operation is to be performed; ii. responsive to the option bit indicating that the clear by address space control element operation is to be performed, clearing the TLB, independent of the content of the first register, of those entries in which the address translation table origin of a translation table was used to create the entries in the TLB corresponds to the address translation table origin in the third register; iii. responsive to the option bit indicating that the clear by address space control element operation is not to be performed, invalidating the range of address translation table entries of a translation table identified by the range field, and clearing the TLB entries corresponding to the invalidated entries.

    Invalidating storage, clearing buffer entries
    34.
    发明专利
    Invalidating storage, clearing buffer entries 未知

    公开(公告)号：GB2413876B

    公开(公告)日：2006-03-01

    申请号：GB0516192

    申请日：2004-05-06

    Applicant: IBM

    Inventor： SLEGEL TIMOTHY JOHN ,  HELLER LISA ,  PFEFFER ERWIN ,  PLAMBECK KENNETH

    IPC: G06F12/08 ,  G06F9/30 ,  G06F9/38 ,  G06F12/10

    Abstract: A method for invalidating translation table entries and clearing corresponding dynamic address translation (DAT) table entries of a translation lookaside buffer (TLB) associated with a processing unit in a computer system, the computer system comprising one or more address translation tables providing translation information to translate virtual addresses to real addresses, wherein address translation table entry information is maintained in the TLB, the method comprising: a) fetching for execution a multifunction Invalidate DAT Table Entry (IDTE) machine instruction, the IDTE instruction comprising an opcode field identifying said instruction and an information field comprising: 1) a first register field for identifying a first register for indicating an origin and type of an address translation table containing a range of one or more entries to be invalidated, 2) a second register field for identifying a second register for including indices used to select a translation table entry in a type of address translation table indicated by the first register, and an option bit for indicating whether a clear by address space control element (ASCE) operation or an invalidating-and-clearing operation is to be performed, and a range field for identifying a number of additional translation table entries, in the address translation table indicated by the first register, to be invalidated, and 3) a third register field for identifying a third register for indicating an origin and type of address translation table to be used when the clear by address space control element operation is to be performed for only selectively clearing TLB entries; and b) executing the fetched IDTE machine instruction, the executing step comprising: i. determining, from the option bit in the second register, whether a clear by address space control element operation is to be performed; ii. responsive to the option bit indicating that the clear by address space control element operation is to be performed, clearing the TLB, independent of the content of the first register, of those entries in which the address translation table origin of a translation table was used to create the entries in the TLB corresponds to the address translation table origin in the third register; iii. responsive to the option bit indicating that the clear by address space control element operation is not to be performed, invalidating the range of address translation table entries of a translation table identified by the range field, and clearing the TLB entries corresponding to the invalidated entries.

    Invalidating entries in a Page Table
    35.
    发明专利
    Invalidating entries in a Page Table 未知

    公开(公告)号：GB2414841A

    公开(公告)日：2005-12-07

    申请号：GB0518901

    申请日：2004-05-06

    Applicant: IBM

    Inventor： SLEGEL TIMOTHY J ,  HELLER LISA ,  PFEFFER ERWIN ,  PLAMBECK KENNETH

    IPC: G06F9/30 ,  G06F9/38 ,  G06F12/08 ,  G06F12/10

    Abstract: Selected units of storage, such as segments of storage or regions of storage, are invalidated. The invalidation is facilitated by the setting of invalidation indicators located in data structure entries corresponding to the units of storage to be invalidated. Additionally, buffer entries associated with the invalidated units of storage or other chosen units of storage are cleared. An instruction is provided to perform the invalidation and/or clearing. Moreover, buffer entries associated with a particular address space are cleared, without any invalidation. This is also performed by the instruction. The instruction can be implemented in software, hardware, firmware or some combination thereof, or it can be emulated.

    ΔΥΝΑΜΙΚΗ ΜΕΤΑΦΡΑΣΗ ΔΙΕΥΘΥΝΣΗΣ ΜΕ ΑΞΙΟΛΟΓΗΣΗ ΕΞΑΙΡΕΣΗΣ ΜΕΤAΦΡΑΣΗΣ
    36.
    发明专利
    ΔΥΝΑΜΙΚΗ ΜΕΤΑΦΡΑΣΗ ΔΙΕΥΘΥΝΣΗΣ ΜΕ ΑΞΙΟΛΟΓΗΣΗ ΕΞΑΙΡΕΣΗΣ ΜΕΤAΦΡΑΣΗΣ 未知

    公开(公告)号：CY1112693T1

    公开(公告)日：2016-02-10

    申请号：CY121100374

    申请日：2012-04-20

    Applicant: IBM

    Inventor： GREINER DAN ,  HELLER LISA ,  OSISEK DAMIAN ,  PFEFFER ERWIN

    IPC: G06F12/10

    Abstract: Δίδεταιμίαεγκατάστασηενισχυμένηςδυναμικήςμετάφρασηςδιεύθυνσης. Σεμίαμορφήπραγματοποίησης, λαμβάνονταιμίαεικονικήδιεύθυνσηπουπρόκειταιναμεταφραστείκαιμίααρχικήδιεύθυνσηπροέλευσηςενόςπίνακαμετάφρασηςτηςιεραρχίαςτωνπινάκωνμετάφρασης. Ηδυναμικήμετάφρασηδιεύθυνσηςτηςεικονικήςδιεύθυνσηςσυνεχίζεται. Σεαπόκρισηπροςμίαδιακοπήμετάφρασης, πουπαρουσιάστηκεκατάτηδιάρκειατηςδυναμικήςμετάφρασηςδιεύθυνσης, αποθηκεύονται bit σεέναπεδίοαξιολόγησηςεξαίρεσηςμετάφρασης (ΤΧQ), ώστεναδεικνύεταιότιη εξαίρεσηείναιείτεμίαεξαίρεση DΑΤπουπαρουσιάστηκεκατάτηνεκτέλεσηενόςπρογράμματοςξενιστήείτεμίαεξαίρεση DΑΤξενιστήπουπαρουσιάστηκεκατάτηνεξαίρεσηενόςφιλοξενούμενουπρογράμματος. ΗΤΧQ είναιεπιπλέονικανήναδείχνειότιη εξαίρεσησυνδυάζεταιμεμίαεικονικήδιεύθυνσηξενιστή, ηοποίαπαράγεταιαπόμίαπραγματικήδιεύθυνσηπλαισίουσελίδαςφιλοξενούμενουή μίααπόλυτηδιεύθυνσηπλαισίουτμήματοςφιλοξενούμενου. ΗΤΧQ είναιεπιπλέονικανήναδείχνειότιείναιπροτιμητέοέναμεγαλύτεροή έναμικρότερομέγεθοςπλαισίουξενιστήγιαναυποστηρίξειέναπλαίσιοφιλοξενούμενου.

    ΑΚΥΡΩΣΗ ΑΠΟΘΗΚΕΥΣΗΣ, ΚΑΘΑΡΙΣΜΟΣ ΚΑΤΑΧΩΡΗΣΕΩΝ ΤΩΝ ΘΕΣΕΩΝ ΠΡΟΣΚΑΙΡΗΣ ΑΠΟΘΗΚΕΥΣΗΣ
    37.
    发明专利
    ΑΚΥΡΩΣΗ ΑΠΟΘΗΚΕΥΣΗΣ, ΚΑΘΑΡΙΣΜΟΣ ΚΑΤΑΧΩΡΗΣΕΩΝ ΤΩΝ ΘΕΣΕΩΝ ΠΡΟΣΚΑΙΡΗΣ ΑΠΟΘΗΚΕΥΣΗΣ 未知

    公开(公告)号：CY1111421T1

    公开(公告)日：2015-08-05

    申请号：CY101101184

    申请日：2010-12-22

    Applicant: IBM

    Inventor： SLEGEL TIMOTHY ,  HELLER LISA ,  PFEFFER ERWIN ,  PLAMBECK KENNETH

    IPC: G06F9/312 ,  G06F9/30 ,  G06F9/38 ,  G06F12/08 ,  G06F12/10

    Abstract: Επιλεγείσεςμονάδεςαποθήκευσης, όπωςτμήματααποθήκευσηςή περιοχέςαποθήκευσης, ακυρώνονται. Ηακύρωσηδιευκολύνεταιμετηρύθμισηδεικτώνακύρωσηςτοποθετημένωνστιςκαταχωρήσειςτηςδομήςδεδομένωνπουαντιστοιχούνστιςμονάδεςαποθήκευσηςπουθαακυρωθούν. Επιπροσθέτως, καταχωρήσειςπρόσκαιρηςαποθήκευσηςή άλλεςεπιλεγόμενεςμονάδεςαποθήκευσηςκαθαρίζονται. Παρέχεταιοδηγίαγιαναδιεξάγεταιη ακύρωσηή/καιο καθαρισμός. Επιπλέον, καταχωρήσειςπρόσκαιρηςαποθήκευσηςπουσυνδυάζονταιμεσυγκεκριμένοχώροδιεύθυνσηςκαθαρίζονταιχωρίςοποιαδήποτεακύρωση. Αυτόεπίσηςδιεξάγεταιμετηνοδηγία. Ηοδηγίαμπορείναπραγματοποιηθείσελογισμικό, σεμηχάνημαυπολογιστή, σεπρογράμματααναχαίτισηςή κάποιοσυνδυασμόαυτώνή μπορείνααντιγράφεται.

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