公开(公告)号：DE602004032035D1

公开(公告)日：2011-05-12

申请号：DE602004032035

申请日：2004-08-04

Applicant: IBM

Inventor： CHEN HUAJIE ,  CHIDAMBARRAO DURESETI ,  GLUSCHENKOV OLEG G ,  STEEGEN AN L ,  YANG HAINING S

IPC: H01L31/0328 ,  H01L21/20 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12

公开(公告)号：SG160376A1

公开(公告)日：2010-04-29

申请号：SG2010016079

申请日：2007-07-31

Applicant: CHARTERED SEMICONDUCTOR MFG ,  IBM

Inventor： WENHE LIN ,  MANN RANDY WILLIAM ,  SHAFER PADRAIC C ,  BAIOCCO CHRISTOPHER VINCENT ,  ZHIJOING LUO ,  YANG HAINING S ,  XIANGDONG CHEN

Abstract: Some non-limiting example embodiments comprise a disposable spacer formation and removal process and a stress capping layer process. We provide a gate structure over a substrate. We form disposable spacers abutting the at least one gate sidewall. We form SID regions adjacent the disposable spacers. We remove the disposable spacers. We can form silicide regions over the SID and gate. In an aspect, we can deposit a stress inducing layer over the gate and surface portions of the substrate adjacent to the gate, wherein the stress inducing liner provides a stress to a portion of the substrate underlying the gate electrode. Fig. 7B

公开(公告)号：SG158179A1

公开(公告)日：2010-01-29

申请号：SG2009086273

申请日：2006-01-09

Applicant: IBM ,  CHARTERED SEMICONDUCTOR MFG

Inventor： YANG HAINING S ,  CHEN XIANGDONG ,  LEE YONG MENG ,  LIN WENHE

Abstract: A method of reducing hot carrier degradation and a semiconductor structure so formed are disclosed. One embodiment of the method includes depositing a silicon nitride layer (40) over a transistor device (10A, 10B), ion implanting (44) a species (48) into the silicon nitride layer (40) to drive hydrogen from the silicon nitride layer (40), and annealing (60) to diffuse the hydrogen into a channel region of the transistor device (10A, 10B). The species (48) may be chosen from, for example: germanium (Ge), arsenic (As), xenon (Xe), nitrogen (N), oxygen (0), carbon (C), boron (B), indium (In), argon (Ar), helium (He), and deuterium (De). The ion implantation (44) modulates atoms in the silicon nitride layer (40) such as hydrogen, nitrogen and hydrogen-nitrogen bonds such that hydrogen can be controllably diffused into the channel region (30).

公开(公告)号：SG144775A1

公开(公告)日：2008-08-28

申请号：SG2007006893

申请日：2007-02-02

Applicant: IBM ,  CHARTERED SEMICONDUCTOR MFG

Inventor： CHAN VICTOR W C ,  YANG HAINING S ,  LEE YONG MENG ,  LIM ENG HUA

Abstract: DUAL-HYBRID LINER FORMATION WITHOUT EXPOSING SILICIDE LAYER TO PHOTORESIST STRIPPING CHEMICALS Methods of fabricating a semiconductor device including a dual-hybrid liner in which an underlying silicide layer (68) is protected from photoresist stripping chemicals by using a hard mask (110) as a pattern during etching, rather than using a photoresist. The hard mask (110) prevents exposure of a silicide layer (68) to photoresist stripping chemicals and provides very good lateral dimension control such that the two nitride liners are well aligned.

公开(公告)号：SG133477A1

公开(公告)日：2007-07-30

申请号：SG2006072169

申请日：2006-10-17

Applicant: CHARTERED SEMICONDUCTOR MFG ,  IBM

Inventor： MENG LEE YONG ,  YANG HAINING S ,  CHAN VICTOR

Abstract: A structure and method of fabrication of a semiconductor device having a stress relief layer under a stress layer in one region of a substrate. In a first example, a stress relief layer is formed over a first region of the substrate (e.g., PFET region) and not over a second region (e.g., NFET region). A stress layer is over the stress relief layer in the first region and over the devices and substrate/silicide in the second region. The NFET transistor performance is enhanced due to the overall tensile stress in the NFET channel while the degradation in the PFET transistor performance is reduced/eliminated due to the inclusion of the stress relief layer. In a second example embodiment, the stress relief layer is formed over the second region, but not the first region and the stress of the stress layer is reversed.

公开(公告)号：SG155895A1

公开(公告)日：2009-10-29

申请号：SG2009059312

申请日：2006-10-17

Applicant: CHARTERED SEMICONDUCTOR MFG ,  IBM

Inventor： MENG LEE YONG ,  YANG HAINING S ,  CHAN VICTOR

Abstract: A structure and method of fabrication of a semiconductor device having a stress relief layer under a stress layer in one region of a substrate. In a first example, a stress relief layer is formed over a first region of the substrate (e.g., PFET region) and not over a second region (e.g., NFET region). A stress layer is over the stress relief layer in the first region and over the devices and. substrate/silicide in the second region. The NFET transistor performance is enhanced due to the overall tensile stress in the NFET channel while the degradation in the PFET transistor performance is reduced/eliminated due to the inclusion of the stress relief layer. In a second example embodiment, the stress relief laver is formed over the second region, but not the first region and the stress of the stress layer is reversed.

公开(公告)号：DE602006008017D1

公开(公告)日：2009-09-03

申请号：DE602006008017

申请日：2006-08-22

Applicant: IBM

Inventor： YANG HAINING S

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/49

公开(公告)号：SG139657A1

公开(公告)日：2008-02-29

申请号：SG2007051733

申请日：2007-07-17

Applicant: IBM ,  CHARTERED SEMICONDUCTOR MFG

Inventor： LEE YONG MENG ,  YANG HAINING S ,  CHAN VICTOR W C ,  LIM ENG HUA

Abstract: STRUCTURE AND METHOD TO IMPLEMENT DUAL STRESSOR LAYERS WITH IMPROVED SILICIDE CONTROL An example embodiment for a method of fabrication of a semiconductor device comprises the following. We provide a substrate (10) with a first device region (12) and a second device region (14). We provide a first type FET transistor (48) in the first device region (12) and provide a second type FET transistor (46) in the second device region (14). We form an etch stop layer (65) over the first and second device regions (12, 14) and forming a first stressor layer (66) over the first device region (12). The first stressor layer (66) puts a first type stress on the substrate (10) in the first device region (12). We form a second stressor layer (71) over the second device region (14). The second stressor layer (71) puts a second type stress on the substrate (10) in the second device region (14). Another example embodiment is the structure of a dual stress layer device having an etch stop layer. Fig. 4.

公开(公告)号：SG126872A1

公开(公告)日：2006-11-29

申请号：SG200602424

申请日：2006-04-11

Applicant: IBM ,  CHARTERED SEMICONDUCTOR MFG

Inventor： YANG HAINING S ,  LIM ENG HUA

Abstract: A method for manufacturing a device includes mapping extreme vertical boundary conditions of a mask layer based on vertical edges of a deposited first layer and a second layer. The mask layer is deposited over portions of the second layer based on the mapping step. The exposed area of the second layer is etched to form a smooth boundary between the first layer and the second layer. The resist layer is stripped. The resulting device is an improved PFET device and NFET device with a smooth boundary between the first and second layers such that a contact can be formed at the smooth boundary without over etching other areas of the device.