公开(公告)号：EP1678753A4

公开(公告)日：2008-08-20

申请号：EP04795234

申请日：2004-10-15

Applicant: IBM

Inventor： DORIS BRUCE B ,  GLUSCHENKOV OLEG G

IPC: H01L21/76 ,  H01L20060101 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L21/84 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/66575 ,  H01L29/78 ,  H01L29/7846

Abstract: A semiconductor device and method of manufacture provide an n-channel field effect transistor (nFET) having a shallow trench isolation with overhangs that overhang Si-SiO2 interfaces in a direction parallel to the direction of current flow and in a direction transverse to current flow. The device and method also provide a p-channel field effect transistor (pFET) having a shallow trench isolation with an overhang that overhangs Si-SiO2 interfaces in a direction transverse to current flow. However, the shallow trench isolation for the pFET is devoid of overhangs, in the direction parallel to the direction of current flow.

公开(公告)号：EP1685584A4

公开(公告)日：2008-12-31

申请号：EP04756373

申请日：2004-06-30

Applicant: IBM

Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER H ,  GLUSCHENKOV OLEG G

IPC: H01L21/8238 ,  H01L21/311 ,  H01L21/76 ,  H01L21/82 ,  H01L21/84 ,  H01L27/12 ,  H01L29/10 ,  H01L29/24 ,  H01L29/808

CPC classification number: H01L29/1608 ,  H01L21/8213 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/1095 ,  H01L29/66651 ,  H01L29/7378 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7849 ,  H01L29/8086

Abstract: A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) (25) in a substrate and providing a first material (30) and a second material (40) on the substrate. The first material (30) and the second material (40) are mixed into the substrate by a thermal anneal process to form a first island (50) and second island (55) at an nFET region and a pFET region, respectively. A layer of different material is formed on the first island (50) and the second island (55). The STI relaxes and facilitates the relaxation of the first island (50) and the second island (55). The first material (30) may be deposited or grown Ge material and the second material (40) may deposited or grown Si:C or C. A strained Si layer is formed on at least one of the first island (50) and the second island (55).

公开(公告)号：EP1654770A4

公开(公告)日：2008-07-16

申请号：EP04780054

申请日：2004-08-04

Applicant: IBM

Inventor： CHEN HUAJIE ,  CHIDAMBARRAO DURESETI ,  GLUSCHENKOV OLEG G ,  STEEGEN AN L ,  YANG HAINING S

IPC: H01L31/0328 ,  H01L21/20 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L31/0336

CPC classification number: H01L21/84 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: A p-type field effect transistor (PFET) (10) and an n-type field effect transistor (NFET) (12) of an integrated circuit are provided. A first strain is applied to the channel region (20) of the PFET (10) but not the NFET (12) via a lattice-mismatched semiconductor layer such as silicon germanium disposed in source and drain regions (111) of only the PFET (10) and not of the NFET.(12) A process of making the PFET (10) and NFET (12) is provided. Trenches are etched in the areas to become the source and drain regions (111) of the PFET and a lattice-mismatched silicon germanium layer (121) is grown epitaxially therein to apply a strain to the channel region of the PFET adjacent thereto. A layer of silicon (14) can be grown over the silicon germanium layer (121) and a salicide (68) formed from the layer of silicon to provide low-resistance source and drain regions (111).

公开(公告)号：JP2005217400A

公开(公告)日：2005-08-11

申请号：JP2005011467

申请日：2005-01-19

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHAKRAVARTI ASHIMA B ,  DORIS BRUCE B ,  GHALI ROMANY ,  GLUSCHENKOV OLEG G ,  GRIBELYUK MICHAEL A ,  LEE WOO-HYEONG ,  MADAN ANITA

IPC: C23C16/24 ,  C23C16/46 ,  H01L21/00 ,  H01L21/205 ,  H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

CPC classification number: C23C16/24 ,  C23C16/46 ,  H01L21/28035 ,  H01L21/32055 ,  H01L29/4925

Abstract: PROBLEM TO BE SOLVED: To provide a method of forming a polycrystalline silicon having hyperfine particle sizes.
SOLUTION: The method of forming a polycrystalline silicon having hyperfine particle sizes employs a differential heating of upper and lower surfaces of a substrate of a CVD apparatus, in which the lower surface of the substrate receives considerably more power than the upper surface, preferably more than 75% of the entire power; and in which the substrate is maintained during deposition at a temperature higher than 50°C above 550°C of crystallization temperature of silicon.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 待解决的问题：提供一种形成具有超细粒径的多晶硅的方法。 解决方案：形成具有超细粒度的多晶硅的方法采用CVD装置的基板的上表面和下表面的差加热，其中基板的下表面比上表面受到相当大的功率， 优选超过整个功率的75％; 并且其中在高于硅的结晶温度高于550℃的温度高于50℃的温度下沉积时，保持基板。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2005175495A

公开(公告)日：2005-06-30

申请号：JP2004357623

申请日：2004-12-10

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER H ,  GLUSCHENKOV OLEG G

IPC: H01L21/76 ,  H01L21/20 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/78684

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor structure and a method of manufacturing using tensile stress and compressive stress.
SOLUTION: The method of manufacturing includes a step of forming shallow trench isolation (STI) in a substrate, and a step of providing a first material and a second material on the substrate. The first material and the second material form a first island and a second island at an pFET region and a nFET region, respectively. A tensile hard mask is formed on the first and the second island layers prior to forming finFETs. A Si epitaxial layer is grown on the sidewalls of the finFETs with the hard mask. The hard mask becomes a capping layer, which is under tension, preventing lateral buckling of the nFETfin.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供使用拉伸应力和压缩应力的半导体结构和制造方法。 解决方案：制造方法包括在衬底中形成浅沟槽隔离（STI）的步骤，以及在衬底上提供第一材料和第二材料的步骤。 第一材料和第二材料分别在pFET区和nFET区形成第一岛和第二岛。 在形成finFET之前，在第一和第二岛层上形成拉伸硬掩模。 在具有硬掩模的finFET的侧壁上生长Si外延层。 硬掩模成为一个处于张力下的覆盖层，可防止nFETfin的横向屈曲。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2005094005A

公开(公告)日：2005-04-07

申请号：JP2004266297

申请日：2004-09-14

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHENG KANGGUO ,  CHIDAMBARRAO DURESETI ,  DIVAKARUNI RAMA ,  GLUSCHENKOV OLEG G

IPC: H01L21/8242 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L27/108 ,  H01L29/78

CPC classification number: H01L27/10864 ,  H01L27/10867 ,  H01L27/10876 ,  H01L27/10888

Abstract: PROBLEM TO BE SOLVED: To provide a method and structure of a vertical strained silicon device.
SOLUTION: A trench capacitor vertical-transistor DRAM cell in an SiGe wafer compensates for overhang of a pad nitride, by forming an epitaxial strained silicon layer on trench walls that improves transistor mobility, removes voids from the polysilicon filling, and reduces resistance on the bit line contact. Another feature is that by forming a vertical strained silicon channel, the performance of the vertical device is improved.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供垂直应变硅器件的方法和结构。 解决方案：SiGe晶片中的沟槽电容器垂直晶体管DRAM单元通过在沟槽壁上形成外延应变硅层来补偿衬垫氮化物的突出，从而提高晶体管的迁移率，去除多晶硅填充物的空隙，并降低电阻 在位线上联系。 另一个特征是通过形成垂直应变硅通道，提高了垂直装置的性能。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：WO2005017964A2

公开(公告)日：2005-02-24

申请号：PCT/US2004025152

申请日：2004-08-04

Applicant: IBM ,  CHEN HUAJIE ,  CHIDAMBARRAO DURESETI ,  GLUSCHENKOV OLEG G ,  STEEGEN AN L ,  YANG HAINING S

Inventor： CHEN HUAJIE ,  CHIDAMBARRAO DURESETI ,  GLUSCHENKOV OLEG G ,  STEEGEN AN L ,  YANG HAINING S

IPC: H01L21/20 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L

CPC classification number: H01L21/84 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: A p-type field effect transistor (PFET) and an n-type field effect transistor (NFET) of an integrated circuit are provided. A first strain is applied to the channel region of the PFET but not the NFET via a lattice-mismatched semiconductor layer such as silicon germanium disposed in source and drain regions of only the PFET and not of the NFET. A process of making the PFET and NFET is provided. Trenches are etched in the areas to become the source and drain regions of the PFET and a lattice-mismatched silicon germanium layer is grown epitaxially therein to apply a strain to the channel region of the PFET adjacent thereto. A layer of silicon can be grown over the silicon germanium layer and a salicide formed from the layer of silicon to provide low-resistance source and drain regions.

Abstract translation: 提供集成电路的p型场效应晶体管（PFET）和n型场效应晶体管（NFET）。 第一应变施加到PFET的沟道区，而不是NFET通过位于仅仅PFET而不是NFET的源极和漏极区域中的晶格不匹配的半导体层，例如硅锗。 提供制造PFET和NFET的工艺。 在区域中蚀刻沟槽以成为PFET的源极和漏极区域，并且将晶格失配的硅锗层外延生长以向与其相邻的PFET的沟道区域施加应变。 可以在硅锗层上生长一层硅层，并从硅层形成硅化物以提供低电阻源极和漏极区域。

公开(公告)号：WO2005057612A3

公开(公告)日：2008-01-03

申请号：PCT/US2004020904

申请日：2004-06-30

Applicant: IBM ,  CHIDAMBARRAO DURESETI ,  DOKUMACI OMER H ,  GLUSCHENKOV OLEG G

Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER H ,  GLUSCHENKOV OLEG G

IPC: H01L21/8238 ,  H01L21/311 ,  H01L21/76 ,  H01L21/82 ,  H01L21/84 ,  H01L27/12 ,  H01L29/24 ,  H01L29/808

CPC classification number: H01L29/1608 ,  H01L21/8213 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/1095 ,  H01L29/66651 ,  H01L29/7378 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7849 ,  H01L29/8086

Abstract: A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) (25) in a substrate and providing a first material (30) and a second material (40) on the substrate. The first material (30) and the second material (40) are mixed into the substrate by a thermal anneal process to form a first island (50) and second island (55) at an nFET region and a pFET region, respectively. A layer of different material is formed on the first island (50) and the second island (55). The STI relaxes and facilitates the relaxation of the first island (50) and the second island (55). The first material (30) may be deposited or grown Ge material and the second material (40) may deposited or grown Si:C or C. A strained Si layer is formed on at least one of the first island (50) and the second island (55).

Abstract translation: 提供半导体结构和制造方法。 制造方法包括在衬底中形成浅沟槽隔离（STI）（25），并在衬底上提供第一材料（30）和第二材料（40）。 通过热退火工艺将第一材料（30）和第二材料（40）混合到衬底中，以在nFET区域和pFET区域分别形成第一岛（50）和第二岛（55）。 在第一岛（50）和第二岛（55）上形成不同材料层。 STI放松并促进第一个岛屿（50）和第二个岛屿（55）的放松。 可以将第一材料（30）沉积或生长Ge材料，并且第二材料（40）可以沉积或生长Si：C或C.在第一岛（50）和第二岛（50）中的至少一个上形成应变Si层 岛（55）。

公开(公告)号：WO2005038875A3

公开(公告)日：2005-08-25

申请号：PCT/US2004034047

申请日：2004-10-15

Applicant: IBM ,  DORIS BRUCE B ,  GLUSCHENKOV OLEG G

Inventor： DORIS BRUCE B ,  GLUSCHENKOV OLEG G

IPC: H01L20060101 ,  H01L21/336 ,  H01L21/76 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L21/84 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/66575 ,  H01L29/78 ,  H01L29/7846

Abstract: A semiconductor device and method of manufacture provide an n-channel field effect transistor (nFET) having a shallow trench isolation with overhangs that overhang Si-SiO2 interfaces in a direction parallel to the direction of current flow and in a direction transverse to current flow. The device and method also provide a p-channel field effect transistor (pFET) having a shallow trench isolation with an overhang that overhangs Si-SiO2 interfaces in a direction transverse to current flow. However, the shallow trench isolation for the pFET is devoid of overhangs, in the direction parallel to the direction of current flow.

Abstract translation: 半导体器件和制造方法提供具有浅沟槽隔离的n沟道场效应晶体管（nFET），其具有在与电流流动方向平行的方向上并且横向于电流的方向上突出的Si-SiO 2界面。 器件和方法还提供具有浅沟槽隔离的p沟道场效应晶体管（pFET），其具有在横向于电流的方向上突出Si-SiO 2界面的突出端。 然而，pFET的浅沟槽隔离在平行于电流方向的方向上没有突出端。

公开(公告)号：AT504078T

公开(公告)日：2011-04-15

申请号：AT04780054

申请日：2004-08-04

Applicant: IBM

Inventor： CHEN HUAJIE ,  CHIDAMBARRAO DURESETI ,  GLUSCHENKOV OLEG G ,  STEEGEN AN ,  YANG HAINING

IPC: H01L21/336 ,  H01L21/20 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12

Abstract: A process is provided for making a PFET and an NFET. Areas in a first semiconductor region adjacent to a gate stack are recessed. A lattice-mismatched semiconductor layer is grown in the recesses to apply a strain to the channel region of the PFET adjacent thereto. A layer of the first semiconductor material can be grown over the lattice-mismatched semiconductor layer and a salicide formed from the layer of silicon to provide low-resistance source and drain regions.