公开(公告)号：EP1805796A4

公开(公告)日：2008-10-01

申请号：EP05800298

申请日：2005-09-29

Applicant: IBM ,  TOSHIBA KK

Inventor： CHEN HUAJIE ,  CHIDAMBARRAO DURESETI ,  OH SANG-HYUN ,  PANDA SIDDHARTHA ,  RAUSCH WERNER A ,  SATO TSUTOMU ,  UTOMO HENRY K

IPC: H01L21/8238 ,  H01L21/336

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/28052 ,  H01L21/28079 ,  H01L21/7624 ,  H01L29/1045 ,  H01L29/165 ,  H01L29/4933 ,  H01L29/495 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: A field effect transistor (FET) (10) is provided which includes a gate stack (29), a pair of first spacers (32) disposed over sidewalls of the gate stack (29 and a pair of semiconductor alloy regions (39) disposed on opposite sides of and spaced a first distance from the gate stack (29). Source and drain regions (24) of the FET (10) are at least partly disposed in the semiconductor alloy regions (39; and spaced a second distance from the gate stack (29) by a corresponding spacer of the pair of first spacers (32), which may be different from the first distance. The FET (10) may also include second spacers (34) disposed on the first spacers (32), and silicide regions (40) at least partly overlying the semiconductor alloy regions (39), wherein the silicide regions (40) are spacec from the gate stack (29) by the first and second spacers (32, 34).

公开(公告)号：EP1668672A4

公开(公告)日：2008-06-25

申请号：EP04782603

申请日：2004-08-30

Applicant: IBM

Inventor： DOKUMACI OMER ,  CHEN HUAJIE ,  CHIDAMBARRAO DURESETI ,  YANG HAINING S

IPC: H01L29/73 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L29/6653 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833 ,  H01L29/7848

Abstract: A structure and method are provided in which an n-type field effect transistor (NFET) and a p-type field effect transistor (PFET) each have a channel region disposed in a single-crystal layer of a first semiconductor and a stress is applied at a first magnitude to a channel region of the PFET but not at that magnitude to the channel region of the NFET. The stress is applied by a layer of a second semiconductor which is lattice-mismatched to the first semiconductor. The layer of second semiconductor is formed over the source and drain regions and extensions of the PFET at a first distance from the channel region of the PFET and is formed over the source and drain regions of the NFET at a second, greater distance from the channel region of the NFET, or not formed at all in the NFET.

公开(公告)号：EP1790003A4

公开(公告)日：2011-01-12

申请号：EP05784302

申请日：2005-08-04

Applicant: IBM

Inventor： BEDELL STEPHEN W ,  CHEN HUAJIE ,  FOGEL KEITH ,  MITCHELL RYAN M ,  SADANA DEVENDRA K

IPC: H01L21/36 ,  H01L21/02 ,  H01L21/20 ,  H01L31/117

CPC classification number: H01L29/1054 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02507 ,  H01L21/02532

公开(公告)号：JP2006032962A

公开(公告)日：2006-02-02

申请号：JP2005204182

申请日：2005-07-13

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BEDELL STEPHEN W ,  CHEN HUAJIE ,  FOGEL KEITH E ,  SADANA DEVENDRA K ,  SHAHIDI GHAVAM G

IPC: H01L21/20

CPC classification number: H01L21/26506 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02694

Abstract: PROBLEM TO BE SOLVED: To provide a method for suppressing the formation of flat surface defects, such as stacking faults and microtwins in a relaxed SiGe alloy layer.
SOLUTION: There is disclosed the method of manufacturing a substantially-relaxed SiGe alloy layer, in which flat surface defect density is decreased. The method comprises the steps of forming a strained Ge-containing layer on the front surface of an Si-containing substrate, implanting ions into the interface of the Ge-containing layer/the Si-containing substrate or under the interface, and forming the substantially-relaxed SiGe alloy layer, in which the flat surface defect density is decreased. Further, there are also provided a substantially relaxed SiGe-on-insulator, having an SiGe layer in which the flat surface defect density is decreased, and a heterostructure comprising the insulator.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种抑制在弛豫SiGe合金层中形成平坦表面缺陷的方法，例如层叠缺陷和微丝。 解决方案：公开了制造基本上松弛的SiGe合金层的方法，其中平坦表面缺陷密度降低。 该方法包括以下步骤：在含Si衬底的前表面上形成应变的含锗层，将离子注入含Ge层/含Si衬底的界面或界面之下，并形成基本上 不透明的SiGe合金层，其中平坦表面缺陷密度降低。 此外，还提供了具有其中平坦表面缺陷密度降低的SiGe层和包含绝缘体的异质结构的基本上松弛的绝缘体上SiGe。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2003332462A

公开(公告)日：2003-11-21

申请号：JP2003109064

申请日：2003-04-14

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： MOCUTA ANDA C ,  IEONG MEIKEI ,  AMOS RICKY S ,  DAINE C BOYD ,  MOCUTA DAN M ,  CHEN HUAJIE

IPC: H01L29/423 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49

CPC classification number: H01L21/823807 ,  H01L21/823828

Abstract: PROBLEM TO BE SOLVED: To provide a high performance (surface channel) CMOS device provided with a mid gap work function metal gate.
SOLUTION: An epitaxial layer is used for adjustment/reduction of a threshold voltage V
t of PFET region and large amount of reduction in V
t (up to 500 mV) which are required by a CMOS device provided with a mid gap metal gate. In this case, the counter doping using an in-site B (boron) doped epitaxial layer or B and C (carbon) codoped epitaxial layer is provided. Here, the doping of C is important to give a surface channel CMOS device provided with the mid gap metal gate while an excellent short channel effect is maintained by holding the shallow B profile through the additional degree of freedom to relaxing the diffusion of B (even in the case of the subsequent activation heat cycle).
COPYRIGHT: (C)2004,JPO

Abstract translation: 要解决的问题：提供一种具有中间间隙功能金属栅极的高性能（表面通道）CMOS器件。 解决方案：使用外延层来调整/降低PFET区域的阈值电压V t ，并且V T 的大量还原（高达500mV ），这是由设置有中间间隙金属栅极的CMOS器件所需要的。 在这种情况下，提供使用现场B（硼）掺杂外延层或B和C（碳）共掺杂外延层的反掺杂。 这里，C的掺杂对于提供具有中间间隙金属栅极的表面沟道CMOS器件而言是重要的，同时通过保持浅的B分布通过附加的自由度来放宽B的扩散（甚至 在随后的活化热循环的情况下）。 版权所有（C）2004，JPO

公开(公告)号：WO2005055290A3

公开(公告)日：2005-09-09

申请号：PCT/EP2004053204

申请日：2004-12-01

Applicant: IBM ,  IBM UK ,  BEDELL STEPHEN ,  COHEN GUY ,  CHEN HUAJIE

Inventor： BEDELL STEPHEN ,  COHEN GUY ,  CHEN HUAJIE

IPC: H01L21/20 ,  H01L21/324 ,  H01L21/762

CPC classification number: H01L21/324

Abstract: A method of fabricating a strained semiconductor-on-insulator (SSOI) substrate in which the strained semiconductor is a thin semiconductor layer having a thickness of less than 50 nm that is located directly atop an insulator layer of a preformed silicon-on-insulator substrate is provided. Wafer bonding is not employed in forming the SSOI substrate of the present invention.

Abstract translation: 一种制造应变半导体绝缘体（SSOI）衬底的方法，其中应变半导体是厚度小于50nm的薄半导体层，其直接位于预成型的绝缘体上硅衬底上的绝缘体层的顶部 被提供。 在形成本发明的SSOI基板时不使用晶片接合。

公开(公告)号：EP1709671A4

公开(公告)日：2010-06-16

申请号：EP04703076

申请日：2004-01-16

Applicant: IBM

Inventor： CHEN HUAJIE ,  BEDELL STEPHEN W ,  SADANA DEVENDRA K ,  MOCUTA DAN M

IPC: H01L21/331 ,  H01L21/20 ,  H01L21/205 ,  H01L21/316 ,  H01L21/762 ,  H01L21/84 ,  H01L29/10 ,  H01L29/786

CPC classification number: H01L21/76256 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/31658 ,  H01L21/84 ,  H01L29/1054 ,  H01L29/78687

公开(公告)号：EP1779422A4

公开(公告)日：2007-08-01

申请号：EP05713741

申请日：2005-02-16

Applicant: IBM

Inventor： CHEN HUAJIE ,  BEDELL STEPHEN W

IPC: H01L21/76 ,  H01L21/205 ,  H01L21/762

CPC classification number: H01L21/76254 ,  Y10S438/91

Abstract: A method is disclosed for forming a semiconductor wafer having a strained Si or SiGe layer on an insulator layer. The method produces a structure having a SiGe buffer layer (43) between the insulator layer (45) and the strained Si/SiGe layer (42), but eliminates the need for Si epitaxy after bonding. The method also eliminates interfacial contamination between strained Si and SiGe buffer layer, and allows the formation of SVSiGe layers having a total thickness exceeding the critical thickness of the strained Si layer.

公开(公告)号：EP1654770A4

公开(公告)日：2008-07-16

申请号：EP04780054

申请日：2004-08-04

Applicant: IBM

Inventor： CHEN HUAJIE ,  CHIDAMBARRAO DURESETI ,  GLUSCHENKOV OLEG G ,  STEEGEN AN L ,  YANG HAINING S

IPC: H01L31/0328 ,  H01L21/20 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L31/0336

CPC classification number: H01L21/84 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: A p-type field effect transistor (PFET) (10) and an n-type field effect transistor (NFET) (12) of an integrated circuit are provided. A first strain is applied to the channel region (20) of the PFET (10) but not the NFET (12) via a lattice-mismatched semiconductor layer such as silicon germanium disposed in source and drain regions (111) of only the PFET (10) and not of the NFET.(12) A process of making the PFET (10) and NFET (12) is provided. Trenches are etched in the areas to become the source and drain regions (111) of the PFET and a lattice-mismatched silicon germanium layer (121) is grown epitaxially therein to apply a strain to the channel region of the PFET adjacent thereto. A layer of silicon (14) can be grown over the silicon germanium layer (121) and a salicide (68) formed from the layer of silicon to provide low-resistance source and drain regions (111).

公开(公告)号：EP1676297A4

公开(公告)日：2008-06-25

申请号：EP04795693

申请日：2004-10-19

Applicant: IBM

Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER ,  CHEN HUAJIE

IPC: H01L21/00 ,  H01L20060101 ,  H01L21/336 ,  H01L21/461 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L27/01 ,  H01L27/12 ,  H01L29/10 ,  H01L31/117

CPC classification number: H01L29/7848 ,  H01L21/3081 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/66628 ,  H01L29/66636 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device and method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET and an nFET. A SiGe layer is selectively grown in the source and drain regions of the pFET channel and a Si:C layer is selectively grown in source and drain regions of the nFET channel. The SiGe and Si:C layer match a lattice network of the underlying Si layer to create a stress component. In one implementation, this causes a compressive component in the pFET channel and a tensile component in the nFET channel.