公开(公告)号：EP1917682A4

公开(公告)日：2009-09-30

申请号：EP06813862

申请日：2006-08-25

Applicant: IBM

Inventor： CHIDAMBARRAO DURESETI ,  ADAM THOMAS N

IPC: H01L29/737 ,  H01L29/161 ,  H01L29/165

CPC classification number: H01L29/7378 ,  H01L29/161 ,  H01L29/165

公开(公告)号：EP1676296A4

公开(公告)日：2008-08-20

申请号：EP04795664

申请日：2004-10-19

Applicant: IBM

Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER

IPC: H01L29/10 ,  H01L20060101 ,  H01L21/00 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/04 ,  H01L29/778 ,  H01L31/036 ,  H01R4/64

CPC classification number: H01L29/1054 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66621 ,  Y10S438/933

Abstract: A semiconductor device and a method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET (40) and an nFET (45). An SiGe layer (45a) is grown in the channel of the nFET channel and a Si:C layer (40a) is grown in the pFET channel. The SiGe and Si:C match lattice network of the underlying Si layer (15) to create a stress component in an overlying grown epitaxial layer (60). In one implementation, this causes a compressive component in the pFET channel and a tensile component in the nFET channel. In further implementation, the SiGe layer grown in both the nFET and pFET channels. In this implementation, the stress level in the pFET channel should be greater than approximately 3 GPa.

公开(公告)号：EP1834350A4

公开(公告)日：2009-06-17

申请号：EP05853245

申请日：2005-12-08

Applicant: IBM

Inventor： CHIDAMBARRAO DURESETI ,  LI YING ,  MALIK RAJEEV ,  NARASIMHA SHREESH ,  YANG HAINING ,  ZHU HUILONG

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/7843 ,  H01L21/823807 ,  H01L29/66772 ,  Y10S438/938

Abstract: The present invention provides a semiconductor device having dual nitride liners, which provide an increased transverse stress state for at least one FET (300) and methods for the manufacture of such a device. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a first silicon nitride liner (360) to the device and applying a second silicon nitride liner (370) adjacent the fast silicon nitride liner, wherein at least one of the first and second silicon nitride liners induces a transverse stress in a silicon channel (330) beneath at least one of the first and second silicon nitride liner.

公开(公告)号：EP1927128A4

公开(公告)日：2009-01-28

申请号：EP06804017

申请日：2006-09-22

Applicant: IBM

Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER ,  GLUSCHENKOV OLEG ,  BELYANSKY MICHAEL

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/51

CPC classification number: H01L29/512 ,  H01L21/26586 ,  H01L21/31155 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66583

Abstract: The present invention provides a semiconductor structure having at least one CMOS device in which the Miller capacitances, i-e., overlap capacitances, are reduced and the drive current is improved. The inventive structure includes a semiconductor substrate having at least one overlaying gate conductor, each of the at least one overlaying gate conductors has vertical edges; a first gate oxide located beneath the at least one overlaying gate conductor, the first gate oxide not extending beyond the vertical edges of the at least overlaying gate conductor; and a second gate oxide located beneath at least a portion of the at one overlaying gate conductor. In accordance with the present invention, the first gate oxide and the second gate oxide are selected from high k oxide-containing materials and low k oxide-containing materials, and the first gate oxide is higher k than the second gate oxide or vice-versa.

公开(公告)号：EP1805796A4

公开(公告)日：2008-10-01

申请号：EP05800298

申请日：2005-09-29

Applicant: IBM ,  TOSHIBA KK

Inventor： CHEN HUAJIE ,  CHIDAMBARRAO DURESETI ,  OH SANG-HYUN ,  PANDA SIDDHARTHA ,  RAUSCH WERNER A ,  SATO TSUTOMU ,  UTOMO HENRY K

IPC: H01L21/8238 ,  H01L21/336

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/28052 ,  H01L21/28079 ,  H01L21/7624 ,  H01L29/1045 ,  H01L29/165 ,  H01L29/4933 ,  H01L29/495 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: A field effect transistor (FET) (10) is provided which includes a gate stack (29), a pair of first spacers (32) disposed over sidewalls of the gate stack (29 and a pair of semiconductor alloy regions (39) disposed on opposite sides of and spaced a first distance from the gate stack (29). Source and drain regions (24) of the FET (10) are at least partly disposed in the semiconductor alloy regions (39; and spaced a second distance from the gate stack (29) by a corresponding spacer of the pair of first spacers (32), which may be different from the first distance. The FET (10) may also include second spacers (34) disposed on the first spacers (32), and silicide regions (40) at least partly overlying the semiconductor alloy regions (39), wherein the silicide regions (40) are spacec from the gate stack (29) by the first and second spacers (32, 34).

公开(公告)号：EP1825509A4

公开(公告)日：2009-04-15

申请号：EP05853786

申请日：2005-12-13

Applicant: IBM

Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER H ,  DORIS BRUCE B ,  GLUSCHENKOV OLEG ,  ZHU HUILONG

IPC: H01L21/84 ,  H01L27/01

CPC classification number: H01L21/84 ,  H01L27/1203 ,  H01L29/7843 ,  Y10S438/938

Abstract: The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate; a first layered stack atop the substrate, the first layered stack comprising a compressive dielectric layer atop the substrate and a first semiconducting layer atop the compressive dielectric layer, wherein the compressive dielectric layer transfers tensile stresses to the first semiconducting layer, and a second layered stack atop the substrate, the second layered stack comprising an tensile dielectric layer atop the substrate and a second semiconducting layer atop the tensile dielectric layer, wherein the tensile dielectric layer transfers compressive stresses to the second semiconducting layer. The tensile dielectric layer and the compressive dielectric layer preferably comprise nitride, such as Si3N4.

公开(公告)号：EP1685584A4

公开(公告)日：2008-12-31

申请号：EP04756373

申请日：2004-06-30

Applicant: IBM

Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER H ,  GLUSCHENKOV OLEG G

IPC: H01L21/8238 ,  H01L21/311 ,  H01L21/76 ,  H01L21/82 ,  H01L21/84 ,  H01L27/12 ,  H01L29/10 ,  H01L29/24 ,  H01L29/808

CPC classification number: H01L29/1608 ,  H01L21/8213 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/1095 ,  H01L29/66651 ,  H01L29/7378 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7849 ,  H01L29/8086

Abstract: A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) (25) in a substrate and providing a first material (30) and a second material (40) on the substrate. The first material (30) and the second material (40) are mixed into the substrate by a thermal anneal process to form a first island (50) and second island (55) at an nFET region and a pFET region, respectively. A layer of different material is formed on the first island (50) and the second island (55). The STI relaxes and facilitates the relaxation of the first island (50) and the second island (55). The first material (30) may be deposited or grown Ge material and the second material (40) may deposited or grown Si:C or C. A strained Si layer is formed on at least one of the first island (50) and the second island (55).

公开(公告)号：EP1668672A4

公开(公告)日：2008-06-25

申请号：EP04782603

申请日：2004-08-30

Applicant: IBM

Inventor： DOKUMACI OMER ,  CHEN HUAJIE ,  CHIDAMBARRAO DURESETI ,  YANG HAINING S

IPC: H01L29/73 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L29/6653 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833 ,  H01L29/7848

Abstract: A structure and method are provided in which an n-type field effect transistor (NFET) and a p-type field effect transistor (PFET) each have a channel region disposed in a single-crystal layer of a first semiconductor and a stress is applied at a first magnitude to a channel region of the PFET but not at that magnitude to the channel region of the NFET. The stress is applied by a layer of a second semiconductor which is lattice-mismatched to the first semiconductor. The layer of second semiconductor is formed over the source and drain regions and extensions of the PFET at a first distance from the channel region of the PFET and is formed over the source and drain regions of the NFET at a second, greater distance from the channel region of the NFET, or not formed at all in the NFET.

公开(公告)号：EP1565931A4

公开(公告)日：2006-04-19

申请号：EP02791319

申请日：2002-11-25

Applicant: IBM

Inventor： DORIS BRUCE B ,  CHIDAMBARRAO DURESETI ,  IEONG MEIKEI ,  MANDELMAN JACK A

IPC: H01L21/00 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L21/823807 ,  H01L21/823828 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7843

Abstract: A semiconductor device structure, includes a PMOS device (200) and an NMOS device (300) disposed on a substrate (1, 2) the PMOS device including a compressive layer (6) stressing an active region of the PMOS device, the NMOS device including a tensile layer (9) stressing an active region of the NMOS device, wherein the compressive layer includes a first dielectric material, the tensile layer includes a second dielectric material, and the PMOS and NMOS devices are FinFET devices (200, 300).

公开(公告)号：EP1711966A4

公开(公告)日：2011-02-16

申请号：EP04704467

申请日：2004-01-22

Applicant: IBM

Inventor： BEINTNER JOCHEN ,  CHIDAMBARRAO DURESETI ,  DIVKARUNI RAMACHANDRA

IPC: H01L29/786 ,  H01L21/336 ,  H01L21/8238

CPC classification number: H01L29/78642 ,  H01L21/2257 ,  H01L29/66787