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    CAPACITOR AND FORMING METHOD THEREOF
    31.
    发明专利
    CAPACITOR AND FORMING METHOD THEREOF 失效

    公开(公告)号：JP2001223340A

    公开(公告)日：2001-08-17

    申请号：JP2001014867

    申请日：2001-01-23

    Applicant: IBM

    Inventor： KERRY BERNSTEIN ,  NICHOLAS THEODORE SCHMIDT ,  STAMPER ANTHONY K ,  STEVEN ARTHUR SAINT ONJI ,  STEVEN HOWARD VOLDMAN

    IPC: H01G4/40 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/822 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/04

    Abstract: PROBLEM TO BE SOLVED: To provide an interconnecting level capacitor structure and a forming method thereof. SOLUTION: The capacitor structure comprises a first insulating layer disposed on an interconnecting level surface of an integrated circuit, first and second conductors which are formed in the first insulating layer and are isolated by a trench delimited by the first insulating layer, a first conductive barrier layer which is disposed on the first and second conductors and connects the first and second conductors, a second insulting layer disposed on the first conductive barrier layer, a second conductive barrier layer disposed on the second insulating layer, and a third conductor which is disposed in the trench and on the second conductive barrier layer. A capacitance is increased by using regions on a top surface, a bottom surface, and a side surface of the capacitor structure. It is possible to obtain an on-cap decoupling capacitor having a larger size without sacrificing a precious silicon space.

    FORMATION OF COPPER INTERCONNECTION STRUCTURE
    32.
    发明专利
    FORMATION OF COPPER INTERCONNECTION STRUCTURE 失效

    公开(公告)号：JP2000200832A

    公开(公告)日：2000-07-18

    申请号：JP36394999

    申请日：1999-12-22

    Applicant: IBM

    Inventor： PAUL D AGUNERO ,  REENA P BUCKWALTER ,  JOHN HAMEL ,  BARBARA LUTHER ,  STAMPER ANTHONY K

    IPC: H01L23/522 ,  H01L21/04 ,  H01L21/28 ,  H01L21/318 ,  H01L21/768

    Abstract: PROBLEM TO BE SOLVED: To improve adhesiveness of a deposited inorganic barrier film to a copper surface of a copper interconnection structure by including exposure of a copper layer in an interconnected semiconductor structure to a reducing plasma before the formation of the inorganic barrier film on the copper interconnection structure. SOLUTION: A copper interconnection structure is exposed to a reducing plasma before an inorganic barrier film 24 is deposited. This reducing plasma is a non-oxidizing, i.e., oxygen-atom-free plasma atmosphere. A suitable plasma is selected from H2, N2, NH3, and rare gas, but it is not limited to these. Further, a combination of more than two of these reducing plasmas such as N2 and H2 is intended. N2 and NH3 are very preferable among these reducing plasmas. The adhesiveness of the inorganic barrier layer 24 to copper 20 can be improved by using this reducing plasma exposure process.

    MICRO-ELECTRO-MECHANICAL SYSTEM (MEMS) AND RELATED ACTUATOR BUMPS, METHOD OF MANUFACTURE AND DESIGN STRUCTURES
    33.
    发明申请
    MICRO-ELECTRO-MECHANICAL SYSTEM (MEMS) AND RELATED ACTUATOR BUMPS, METHOD OF MANUFACTURE AND DESIGN STRUCTURES 审中-公开
    微电子机械系统（MEMS）及相关执行机构的制造，制造和设计结构的方法

    公开(公告)号：WO2012177304A3

    公开(公告)日：2014-03-13

    申请号：PCT/US2012029005

    申请日：2012-03-14

    Applicant: IBM ,  JAHNES CHRISTOPHER V ,  STAMPER ANTHONY K

    Inventor： JAHNES CHRISTOPHER V ,  STAMPER ANTHONY K

    IPC: B81B3/00

    CPC classification number: H01H59/0009 ,  B81B3/001 ,  B81B7/0006 ,  B81B2201/016 ,  B81B2203/0118 ,  B81B2203/04 ,  B81C1/0015 ,  B81C1/00293 ,  B81C2203/0145 ,  G06F17/5045 ,  G06F17/5068 ,  H01H1/0036 ,  H01H2001/0057 ,  Y10T29/49121

    Abstract: Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are provided. The method of forming a MEMS structure includes forming fixed actuator electrodes (115) and a contact point on a substrate. The method further includes forming a MEMS beam (100) over the fixed actuator electrodes and the contact point. The method further includes forming an array of actuator electrodes (105') in alignment with portions of the fixed actuator electrodes, which are sized and dimensioned to prevent the MEMS beam from collapsing on the fixed actuator electrodes after repeating cycling. The array of actuator electrodes are formed in direct contact with at least one of an underside of the MEMS beam and a surface of the fixed actuator electrodes.

    Abstract translation: 提供微机电系统（MEMS）结构，制造方法和设计结构。 形成MEMS结构的方法包括在基板上形成固定的致动器电极（115）和接触点。 该方法还包括在固定的致动器电极和接触点上形成MEMS光束（100）。 该方法还包括形成与固定致动器电极的部分对准的致动器电极阵列（105'），其尺寸和尺寸被设计成防止MEMS梁在重复循环之后塌陷在固定的致动器电极上。 致动器电极的阵列形成为与MEMS光束的下侧和固定的致动器电极的表面中的至少一个直接接触。

    PROTECTION AGAINST CHARGING DAMAGE IN HYBRID ORIENTATION TRANSISTORS
    36.
    发明申请
    PROTECTION AGAINST CHARGING DAMAGE IN HYBRID ORIENTATION TRANSISTORS 审中-公开
    防止混合定向晶体管充电损坏

    公开(公告)号：WO2007115146A3

    公开(公告)日：2008-04-24

    申请号：PCT/US2007065604

    申请日：2007-03-30

    Applicant: IBM ,  HOOK TERENCE B ,  MOCUTA ANDA C ,  SLEIGHT JEFFREY W ,  STAMPER ANTHONY K

    Inventor： HOOK TERENCE B ,  MOCUTA ANDA C ,  SLEIGHT JEFFREY W ,  STAMPER ANTHONY K

    IPC: H02H9/00

    CPC classification number: H01L21/84 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0251 ,  H01L27/0629 ,  H01L27/1203 ,  H01L27/1207

    Abstract: A chip includes a CMOS structure having a bulk device (20) disposed in a first region (24) of a semiconductor substrate (50) in conductive communication with an underlying bulk region (18) of the substrate, the first region (24) and the bulk region (20) having a first crystal orientation. A SOI device (10) is disposed in a semiconductor-on-insulator ("SOI") layer (14) separated from the bulk region of the substrate by a buried dielectric layer (16), the SOI layer having a different crystal orientation from the first crystal orientation. In one example, the bulk device includes a p-type field effect transistor ("PFET") and the SOI device includes an n-type field effect transistor ("NFET") device. Alternatively, the bulk device can include an NFET and the SOI device can include a PFET. When the SOI device has a gate conductor (11) in conductive communication with a gate conductor (21) of the bulk device, charging damage can occur to the SOI device, except for the presence of diodes in reverse-biased conductive communication with the bulk region. The diodes are operable to conduct a discharge current to the bulk region when either a voltage on the gate conductor or a voltage on the source or drain region of the SOI device exceeds a diode's breakdown voltage.

    Abstract translation: 芯片包括CMOS结构，该CMOS结构具有布置在半导体衬底（50）的第一区域（24）中的与衬底的下方体区（18）导电连通的体装置（20），第一区域（24）和 该体区域（20）具有第一晶体取向。 SOI器件（10）设置在绝缘体上半导体（“SOI”）层（14）中，所述绝缘体上半导体（SOI）层通过掩埋介电层（16）与衬底的体区分开，SOI层具有与 第一个晶体取向。 在一个示例中，大容量器件包括p型场效应晶体管（“PFET”），并且SOI器件包括n型场效应晶体管（“NFET”）器件。 或者，大容量器件可以包括NFET，并且SOI器件可以包括PFET。 当SOI器件具有与大容量器件的栅极导体（21）导电连通的栅极导体（11）时，除了存在二极管与SOI器件的反向偏置传导通信之外，SOI器件可能会发生充电损坏 地区。 当栅极导体上的电压或SOI器件的源极或漏极区上的电压超过二极管的击穿电压时，二极管可操作以将放电电流传导至体区。

    GAP-TYPE CONDUCTIVE INTERCONNECT STRUCTURES IN SEMICONDUCTOR DEVICE
    37.
    发明申请
    GAP-TYPE CONDUCTIVE INTERCONNECT STRUCTURES IN SEMICONDUCTOR DEVICE 审中-公开
    半导体器件中的GAP型导电互连结构

    公开(公告)号：WO2005117085A3

    公开(公告)日：2006-10-12

    申请号：PCT/US2005018050

    申请日：2005-05-23

    Applicant: IBM ,  STAMPER ANTHONY K

    Inventor： STAMPER ANTHONY K

    IPC: H01L21/311 ,  H01L21/02 ,  H01L21/768

    CPC classification number: H01L21/7682 ,  H01L21/31116 ,  H01L21/76807 ,  H01L28/87

    Abstract: A method of forming a semiconductor device, and the device so formed. Depositing alternating layers of a first dielectric material (12a-f) and a second dielectric material (14a-f), wherein the first and second dielectric materials are selectively etchable at different rates. Forming a first feature (22, 24) within the alternating layers of dielectric material. Selectively etching the alternating layers of dielectric material to remove at least a portion (26) of the first dielectric material in each layer having the first dielectric material and leaving the second dielectric material as essentially unetched.

    Abstract translation: 形成半导体器件的方法以及如此形成的器件。 沉积第一介电材料（12a-f）和第二介电材料（14a-f）的交替层，其中所述第一和第二介电材料可以以不同的速率被选择性地蚀刻。 在电介质材料的交替层内形成第一特征（22,24）。 选择性地蚀刻介电材料的交替层以去除具有第一电介质材料的每层中的第一介电材料的至少一部分（26），并使第二介电材料基本上未被蚀刻。

    REMOVAL OF ETCHING PROCESS RESIDUAL IN SEMICONDUCTOR FABRICATION
    39.
    发明申请
    REMOVAL OF ETCHING PROCESS RESIDUAL IN SEMICONDUCTOR FABRICATION 审中-公开
    在半导体制造中去除蚀刻工艺残留

    公开(公告)号：WO2008091923A3

    公开(公告)日：2009-12-30

    申请号：PCT/US2008051758

    申请日：2008-01-23

    Applicant: IBM ,  HERRIN RUSSELL T ,  LINDGREN PETER J ,  STAMPER ANTHONY K

    Inventor： HERRIN RUSSELL T ,  LINDGREN PETER J ,  STAMPER ANTHONY K

    IPC: C11D7/00

    CPC classification number: H01L23/5223 ,  H01L21/02063 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor structure and methods for forming the same. A semiconductor fabrication method includes steps of providing a structure. A structure incl udes (a) a dielectric layer, (b) a first electrically conductive region buried in the dielectric layer, wherein the first electrically conductive region comprises a first electrically conductive material, and (c) a second electrically conductive region buried in the dielectric layer, wherein the second electrically conductive region comprises a second electrically conductive material being different from the first electrically conductive material. The method further includes the steps of creating a first hole and a second hole in the dielectric layer resulting in the first and second electrically conductive regions being exposed to a surrounding ambient through the first and second holes, respectively. Then, the method further includes the steps of introducing a basic solvent to bottom walls and side walls of the first and second holes.

    Abstract translation: 半导体结构及其形成方法。 半导体制造方法包括提供结构的步骤。 一种结构包括（a）介电层，（b）掩埋在所述电介质层中的第一导电区域，其中所述第一导电区域包括第一导电材料，和（c）第二导电区域， 介电层，其中第二导电区域包括不同于第一导电材料的第二导电材料。 该方法还包括以下步骤：在电介质层中形成第一孔和第二孔，导致第一和第二导电区域分别通过第一孔和第二孔暴露于周围环境。 然后，该方法还包括将碱性溶剂引入第一孔和第二孔的底壁和侧壁的步骤。

    LOW RESISTANCE AND INDUCTANCE BACKSIDE THROUGH VIAS AND METHODS OF FABRICATING SAME
    40.
    发明申请
    LOW RESISTANCE AND INDUCTANCE BACKSIDE THROUGH VIAS AND METHODS OF FABRICATING SAME 审中-公开
    通过VIAS的低电阻和电感及其制造方法

    公开(公告)号：WO2007084879A3

    公开(公告)日：2008-02-21

    申请号：PCT/US2007060544

    申请日：2007-01-15

    Applicant: IBM ,  ERTURK METE ,  GROVES ROBERT A ,  JOHNSON JEFFREY B ,  JOSEPH ALVIN J ,  LIU QIZHI ,  SPROGIS EDMUND J ,  STAMPER ANTHONY K

    Inventor： ERTURK METE ,  GROVES ROBERT A ,  JOHNSON JEFFREY B ,  JOSEPH ALVIN J ,  LIU QIZHI ,  SPROGIS EDMUND J ,  STAMPER ANTHONY K

    IPC: H01L21/00 ,  H01L21/302 ,  H01L21/306 ,  H01L21/44 ,  H01L21/77

    CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A backside contact structure and method of fabricating the structure. The method includes: forming a dielectric isolation (250) in a substrate (100), the substrate (100) having a frontside and an opposing backside; forming a first dielectric layer (105) on the frontside of the substrate (100); forming a trench (265C) in the first dielectric layer (105), the trench (265C) aligned over and within a perimeter of the dielectric isolation (250) and extending to the dielectric isolation (250); extending the trench (265C) formed in the first dielectric layer (1 05) through the dielectric isolation (250) and into the substrate (1 00)to a depth (Dl ) less than a thickness of the substrate (1 00); filling the trench (265C) and co-planarizing a top surface of the trench (265C) with a top surface of the first dielectric layer (1 05) to form an electrically conductive through via (270C); and thinning the substrate (100) from a backside of the substrate (100) to expose the through via (270C).

    Abstract translation: 背面接触结构及其制造方法。 该方法包括：在衬底（100）中形成绝缘隔离（250），所述衬底（100）具有前侧和相对的背面; 在所述基板（100）的前侧形成第一介电层（105）; 在所述第一电介质层（105）中形成沟槽（265C），所述沟槽（265C）在所述电介质隔离（250）的周边内并且在所述绝缘隔离（250）的周边内并且延伸到所述电介质隔离（250）; 将形成在第一电介质层（105）中的沟槽（265C）延伸通过电介质隔离（250）并延伸到衬底（100）中至小于衬底厚度（001）的深度（D1）。 填充沟槽（265C）并且将沟槽（265C）的顶表面与第一介电层（105）的顶表面共平面化以形成导电通孔（270C）; 以及从所述衬底（100）的背面使所述衬底（100）变薄以暴露所述通孔（270C）。

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