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    31.
    发明专利
    未知

    公开(公告)号：DE10150498A1

    公开(公告)日：2003-04-30

    申请号：DE10150498

    申请日：2001-10-12

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： PLAETTNER ECKEHARD ,  FEURLE ROBERT ,  PLAN MANFRED

    IPC: G11C7/06

    Abstract: A semiconductor memory apparatus includes a memory cell array having a multiplicity of data lines and a multiplicity of local amplifiers, each of the local amplifiers being associated with a data line. An amplifier group includes at least two amplifiers selected from the multiplicity of local amplifiers. Each amplifier has at least a pair of selection transistors for selecting a particular amplifier from the amplifier group. The selection transistors have a common gate, an unshared intrinsic diffusion region, and a shared intrinsic diffusion region, the shared intrinsic diffusion region being shared with an adjacent selection transistor from an adjacent amplifier.

    32.
    发明专利
    未知

    公开(公告)号：DE10115816A1

    公开(公告)日：2002-10-10

    申请号：DE10115816

    申请日：2001-03-30

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： TAEUBER ANDREAS ,  DORTU JEAN-MARC ,  SCHMOELZ PAUL ,  FEURLE ROBERT

    IPC: G11C7/22 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/407

    Abstract: In order to operate an integrated dynamic memory having a memory cell array having bit lines and word lines a plurality of individual actions-to be performed for a memory access-from the activation of one of the word lines up to the precharging of the word lines are controlled in a synchronized manner with a clock signal. A value for defining a defined number of clock cycles between at least two individual actions is programmed at the beginning. For this purpose, a control circuit has a programmable unit. In this way, in conjunction with a clocked circuit, a comparatively high data throughput is made possible even at variable clock frequencies.

    33.
    发明专利
    未知

    公开(公告)号：DE10110274A1

    公开(公告)日：2002-09-19

    申请号：DE10110274

    申请日：2001-03-02

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： FEURLE ROBERT

    IPC: G11C8/08 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14 ,  G11C11/407 ,  G11C7/00

    Abstract: What is specified is an integrated memory having a plurality of memory cell arrays that are each assigned row decoders and column decoders. During read or write operations in the present integrated memory, in each case at least two word lines are activated simultaneously, in each case only one bit line being selected simultaneously. Compared with conventional memory architectures, this results in a high data rate even at very high frequencies and with a variable burst length, and additionally in a comparatively low power loss.

    34.
    发明专利
    未知

    公开(公告)号：DE59805044D1

    公开(公告)日：2002-09-05

    申请号：DE59805044

    申请日：1998-11-09

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： FEURLE ROBERT ,  SAVIGNAC DOMINIQUE ,  SCHNEIDER HELMUT

    IPC: G05F3/24 ,  H03K19/0175

    Abstract: A buffer circuit serves for buffering a supply voltage of an integrated circuit. The supply voltage is present between two potential nodes. A series circuit is disposed between the two potential nodes and includes at least two buffer capacitors between which a third potential node is disposed. The third potential node is connected to an additional circuit which influences the potential of the third potential node in such a way that it does not exceed an upper and/or lower limit value when a leakage current occurs through one of the capacitors. The advantage of the buffer circuit is that when there is a defect in just one of the buffer capacitors, the other capacitor is prevented from being destroyed.

    35.
    发明专利
    未知

    公开(公告)号：DE59801722D1

    公开(公告)日：2001-11-15

    申请号：DE59801722

    申请日：1998-11-11

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SAVIGNAC DOMINIQUE ,  FEURLE ROBERT ,  SCHNEIDER HELMUT

    IPC: G11C11/405 ,  G11C5/14 ,  G11C11/4074 ,  H02J9/06

    Abstract: An integrated memory includes two potential nodes at which a supply voltage is present. Memory cells each have a selection transistor and a storage capacitor. At least one series circuit is disposed between the two potential nodes. The series circuits each have at least one buffer capacitor and one associated transistor. The associated transistor effects current limiting in the event of a defect in the at least one buffer capacitor. Each of the buffer capacitor and associated transistor have a mutual configuration and dimensions like the selection transistor and storage capacitor of one of the memory cells and have only an electrical connection differing from the selection transistor and storage capacitor.

    Support structure for semiconductor type stacked fuse
    36.
    发明专利
    Support structure for semiconductor type stacked fuse 未知

    公开(公告)号：DE19946203A1

    公开(公告)日：2001-04-19

    申请号：DE19946203

    申请日：1999-09-27

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SCHNEIDER HELMUT ,  FEURLE ROBERT

    IPC: H01L23/525 ,  H01L27/112

    Abstract: The support structure has a metal track (7) on a lower metallization plane connected with a fuse (12) on a top metallization plane via a contact hole (11). The track is provided on an insulator layer (3) which comprises an embedded gate conductor (4,5,6). The gate conductor (5,9) is provided within the insulator layer below the metal track to be supported. The gate conductor (4,5,6;9) preferably comprises doped polycrystalline silicon.

    37.
    发明专利
    未知

    公开(公告)号：DE50115046D1

    公开(公告)日：2009-10-01

    申请号：DE50115046

    申请日：2001-08-21

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： FEURLE ROBERT ,  SAVIGNAC DOMINIQUE DR

    IPC: G11C11/401 ,  H01L27/108 ,  G11C11/34 ,  G11C11/407 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/06

    Abstract: An integrated store, has storage cells which each comprise a selection transistor and a storage capacitance with each storage cell, the storage capacitance is connected via the selection transistor to one of several column lines (BLK). With each storage cell, a control terminal of the selection transistor is connected to one of several row-lines (WLN) and with the buffer capacitances in each case one contact (K2) is connected to a further one of the column lines (BLK) and the buffer capacitances (CP) are arranged in such a way that the connections (GB) between the respective buffer capacitance and the contact (K2) is arranged parallel to another one of the row-lines (WLK).

    38.
    发明专利
    未知

    公开(公告)号：DE10156749B4

    公开(公告)日：2007-05-10

    申请号：DE10156749

    申请日：2001-11-19

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： FEURLE ROBERT ,  DORTU JEAN-MARC ,  TAEUBER ANDREAS ,  SCHMOELZ PAUL

    IPC: G11C7/10 ,  G06F12/00 ,  G11C11/408

    Abstract: The memory device has a memory area (114) for storing data, an input (126) for receiving a data bundle comprising a number of time-sequential data blocks. A further input (112) receives a data mask signal associated with the data bundle. A device (112) receives one data block to be written into the memory area, independently of the data mask signal. A device writes the received data block into the memory area. Independent claims are also included for the following: (1) a processor system; and (2) a method of performing write operations into a memory area.

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