公开(公告)号：DE102005001253A1

公开(公告)日：2006-07-20

申请号：DE102005001253

申请日：2005-01-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HAPP THOMAS ,  PINNOW CAY-UWE ,  GRUENING ULRIKE VON SCHWERIN

IPC: H01L27/24

Abstract: The memory cell arrangement (1) has lower electrode (BE) and upper electrode (TE) and activated solid electrolyte material area (F) between them as memory material area. The whole of solid electrolyte material area is coherently designed for solid electrolyte memory cell (10). The whole of upper electrode is also coherently designed for the cell. Independent claims are also included for the following: (A) Semiconductor memory; and (B) Method for manufacture of memory cell arrangement.

公开(公告)号：DE102004022604B4

公开(公告)日：2006-06-08

申请号：DE102004022604

申请日：2004-05-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PINNOW CAY-UWE ,  HAPP THOMAS

IPC: H01L27/24 ,  H01L21/283 ,  H01L45/00

Abstract: A process for producing a sublithographic contact structure in a semiconductor element, comprises forming primary and secondary electrical contacts (12,17), and providing one of the contact regions (26,28) with sublithographic dimensions. The dimensions are achieved by a chemical reaction during which at least one of the contact elements is turned into a dielectric.

公开(公告)号：DE102004040751A1

公开(公告)日：2006-03-09

申请号：DE102004040751

申请日：2004-08-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： UFERT KLAUS ,  PINNOW CAY-UWE ,  HAPP THOMAS

IPC: G11C13/02 ,  H01L27/24

Abstract: A nonvolatile, resistively switching memory cell includes a layer arranged between a first electrode and a second electrode. The layer includes one or more chalcogenide compound(s) selected from the group consisting of CuInS, CuInSe, CdInS, CdInSe, ZnInS, MnInS, MnZnInS, ZnInSe, InS, InSSe and InSe, with alkali metal or alkaline-earth metal ions contained in the layer of the chalcogenide compound(s).

公开(公告)号：DE102004041893A1

公开(公告)日：2006-03-02

申请号：DE102004041893

申请日：2004-08-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SYMANCZYK RALF ,  PINNOW CAY-UWE ,  HAPP THOMAS

IPC: H01L21/822 ,  H01L27/24

公开(公告)号：DE102004041191A1

公开(公告)日：2006-03-02

申请号：DE102004041191

申请日：2004-08-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HAPP THOMAS ,  PINNOW CAY-UWE

IPC: G11C13/00 ,  H01L27/24

Abstract: Nonvolatile storage cell with a compound (sic) having a layer contacted via two electrodes, which can be reversibly changed between the amorphous and crystalline states. The electroactive layer is a compound from the group:GaSb, GeSb, GaGeSb, and GaSb and GeSb alloys of given general formula which includes quantities A and y, and also GaGeSb alloys, where A can be any metal and y = 10-15. An independent claim is inluded for preparation of the storage cell involving deposition of the above compound onto an electrode.

公开(公告)号：DE102004040503A1

公开(公告)日：2006-02-23

申请号：DE102004040503

申请日：2004-08-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HAPP THOMAS ,  KUND MICHAEL

IPC: H01L21/50 ,  H01L23/50 ,  H01L23/552 ,  H01L27/24

Abstract: A semiconductor element comprises a chip (1) surrounded by a housing (8) with at least the top and bottom sides of the chip and housing being completely covered or enclosed by a screening layer (12,13) so that the chip is at least partly electrically or magnetically screened. Independent claims are also included for the following: (A) a preparation process as above;and (B) a screening process as above.

公开(公告)号：DE102004035830A1

公开(公告)日：2006-02-16

申请号：DE102004035830

申请日：2004-07-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HAPP THOMAS

IPC: G11C13/00 ,  H01L27/24

Abstract: A memory device is described an active material configured to be placed in a more or less conductive state by means of appropriate switching processes. The active material is positioned between a material having low thermal conductivity or material layers having low thermal conductivity.

公开(公告)号：DE102004019860A1

公开(公告)日：2005-11-17

申请号：DE102004019860

申请日：2004-04-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HAPP THOMAS ,  KUND MICHAEL

IPC: G11C13/02 ,  G11C16/02

公开(公告)号：DE102004014487A1

公开(公告)日：2005-11-17

申请号：DE102004014487

申请日：2004-03-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HAPP THOMAS

IPC: G11C11/46 ,  G11C13/00 ,  H01L21/8234 ,  H01L21/8244 ,  H01L27/108 ,  H01L27/24 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119 ,  H01L45/00

公开(公告)号：DE10345475B4

公开(公告)日：2008-04-17

申请号：DE10345475

申请日：2003-09-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SEIDL HARALD ,  HAPP THOMAS ,  PINNOW CAY-UWE ,  GUTSCHE MARTIN

IPC: H01L27/115 ,  G03G15/02 ,  H01L21/28 ,  H01L29/423 ,  H01L29/788

Abstract: A nonvolatile integrated semiconductor memory has an arrangement of layers with a tunnel barrier layer and a charge-storing level. The charge-storing level has a dielectric material which stores scattered in charge carriers in a spatially fixed position. The tunnel barrier layer has a material through which high-energy charge carriers can tunnel. At least one interface surface of the charge-storing level has a greater microscopic roughness than the interface surface of the tunnel barrier layer, which is remote from the charge-storing level. The charge-storing level has a greater layer thickness in first regions than in second regions. This produces a relatively identical distribution and localization of positive and negative charge carriers in the lateral direction. The charge carriers which are scattered into the charge-storing level, therefore, recombine completely, so that the risk of unforeseen data loss during long-term operation of nonvolatile memories is reduced.