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    31.
    发明专利
    未知

    公开(公告)号：DE102006035039B4

    公开(公告)日：2008-10-30

    申请号：DE102006035039

    申请日：2006-07-28

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SMOLA MICHAEL ,  KNIFFLER OLIVER

    IPC: G06F21/78

    Abstract: The system has a processor (P) e.g. safety-controller, and two non-volatile memory mediums (S1, S2) e.g. multimedia card, where the user data are stored in the memory medium (S1). The management data that are utilized for managing of the user data in the memory medium (S1) are stored in the memory medium (S2). The respective memory mediums are connected with the processor via two respective buses (B1, B2). The processor has two caches (C1, C2) for temporary storage of the user and management data, which are transferred via the buses, respectively. An independent claim is also included for a method of operating a data processing system.

    32.
    发明专利
    未知

    公开(公告)号：DE50014501D1

    公开(公告)日：2007-08-30

    申请号：DE50014501

    申请日：2000-09-20

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SEDLAK HOLGER ,  KNIFFLER OLIVER ,  GAERTNER WOLFGANG

    IPC: G06F13/362

    Abstract: A method of operating a processor bus, with which a central unit (processor) makes accesses to various peripheral units, is described. The processor bus has the ability to change the order of the accesses as a function of the operating state of the peripheral units, and the peripheral units can either reject or delay the access.

    34.
    发明专利
    未知

    公开(公告)号：DE50301830D1

    公开(公告)日：2006-01-12

    申请号：DE50301830

    申请日：2003-04-11

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KLUG FRANZ ,  KNIFFLER OLIVER

    IPC: G06K19/073

    Abstract: Data processing device comprises a data processing module (10) that can be operated in two modes. In the first mode it is operated with normal power use, while in the second mode it operates with reduced or zero power use. A signaler (12) is provided for signaling that the data processing device can be switched into its second mode. Random variation of the operation mode, provided by use of a random number generator in conjunction with the device controller, ensures that the device is protected against differential power analysis. The invention also relates to a corresponding method for operating a data processing device.

    36.
    发明专利
    未知

    公开(公告)号：DE50201842D1

    公开(公告)日：2005-01-27

    申请号：DE50201842

    申请日：2002-04-08

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SEDLAK HOLGER ,  KNIFFLER OLIVER ,  WEDER UWE ,  GUO SHUWEI

    IPC: G06F1/04 ,  G06F1/08 ,  G06F1/32 ,  H03L7/00

    Abstract: A frequency regulating circuit for the current-consumption-dependent clock supply of a circuit configuration includes a current measuring device for measuring the instantaneous current consumption of the circuit configuration, a controllable clock supply circuit, which can be connected to a clock input of the circuit configuration, and a control device for driving the clock supply circuit based upon the measured current consumption, an increase in the current consumption of the circuit configuration effecting a reduction in the clock frequency at the output of the clock supply circuit. Such a circuit ensures that a maximum permissible current consumption is not exceeded, but, at the same time, makes possible a maximum power of the circuit by a maximum clock frequency.

    37.
    发明专利
    未知

    公开(公告)号：BR0209359A

    公开(公告)日：2004-06-08

    申请号：BR0209359

    申请日：2002-04-08

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SEDLAK HOLGER ,  KNIFFLER OLIVER ,  WEDER UWE ,  GUO SHUWEI

    IPC: G06F1/04 ,  G06F1/08 ,  G06F1/32 ,  H03L7/00

    Abstract: A frequency regulating circuit for the current-consumption-dependent clock supply of a circuit configuration includes a current measuring device for measuring the instantaneous current consumption of the circuit configuration, a controllable clock supply circuit, which can be connected to a clock input of the circuit configuration, and a control device for driving the clock supply circuit based upon the measured current consumption, an increase in the current consumption of the circuit configuration effecting a reduction in the clock frequency at the output of the clock supply circuit. Such a circuit ensures that a maximum permissible current consumption is not exceeded, but, at the same time, makes possible a maximum power of the circuit by a maximum clock frequency.

    38.
    发明专利
    未知

    公开(公告)号：DE10217291A1

    公开(公告)日：2003-11-06

    申请号：DE10217291

    申请日：2002-04-18

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KLUG FRANZ ,  KNIFFLER OLIVER

    IPC: G06K19/073 ,  G06F1/26 ,  G06F12/14

    Abstract: Data processing device comprises a data processing module (10) that can be operated in two modes. In the first mode it is operated with normal power use, while in the second mode it operates with reduced or zero power use. A signaler (12) is provided for signaling that the data processing device can be switched into its second mode. Random variation of the operation mode, provided by use of a random number generator in conjunction with the device controller, ensures that the device is protected against differential power analysis. The invention also relates to a corresponding method for operating a data processing device.

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