公开(公告)号：DE10315527B3

公开(公告)日：2004-09-30

申请号：DE10315527

申请日：2003-04-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHAEFER ANDRE

IPC: G11C7/10 ,  H04L25/08 ,  G11C11/401 ,  H03K5/24

Abstract: The circuit has a control stage (25) for generating a control voltage with a voltage generator stage (26) identical to a termination stage (20) producing a comparison voltage and a differential amplifier (27) to which the comparison and reference voltages are input. The control voltage is taken from am amplifier output and applied to control inputs of voltage generator stage first and second resistance elements (23,24) and the termination stage. An independent claim is also included for the following: (a) a method of setting a termination voltage at a termination stage.

公开(公告)号：DE10244516A1

公开(公告)日：2004-04-15

申请号：DE10244516

申请日：2002-09-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHAEFER ANDRE ,  SZCZYPINSKI KAZIMIERZ ,  POLNEY JENS

IPC: H03K19/00 ,  H03K19/0175 ,  H03K19/0185 ,  G11C7/06

Abstract: An integrated circuit, in particular an integrated memory circuit, has an input circuit for the purpose of receiving a signal. The input circuit has an activation input for an activation signal in order to activate the input circuit, in a manner dependent on the activation signal, for the purpose of receiving signals.

公开(公告)号：DE10243604A1

公开(公告)日：2004-04-01

申请号：DE10243604

申请日：2002-09-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHNABEL JOACHIM ,  SCHAEFER ANDRE ,  OBERGRUSBERGER XAVER ,  MOSLER SEBASTIAN

IPC: H01L27/02 ,  H01L27/08 ,  H01L27/105 ,  H01L27/108 ,  H01L27/118

Abstract: The resistors (13a,b,c,d,e) are arranged so that they are staggered w.r.t. each other in the length direction of the resistors. All resistors preferably have the same length, width and depth, and have the same individual resistance values (R). Preferably, there are more than four or five resistors, and they may be alternately staggered towards the front and toward the back. An Independent claim is included for a semiconductor device.

公开(公告)号：DE10131682A1

公开(公告)日：2003-01-16

申请号：DE10131682

申请日：2001-06-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RUCKERBAUER HERMANN ,  SCHAEFER ANDRE

IPC: G11C7/10 ,  H03K5/08 ,  H03K5/125

Abstract: The invention relates to a method and to an input circuit for evaluating a data item in a data signal at an input of a memory component. The data signal is integrated between a start time and an end time that are specified by a control signal. An integration period between the start time and the end time depends on the frequency of the data signal. The data item is assigned a logic data value based on the result of the integration. The input circuit has a comparator device, an integration device and a switching device. The data signal is first integrated in order to obtain an integration value. The comparator device compares the integration value with a prescribed threshold value. A logic data value is assigned to the data item based on the result of the comparison.

公开(公告)号：DE102004061738B4

公开(公告)日：2007-06-28

申请号：DE102004061738

申请日：2004-12-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHAEFER ANDRE

IPC: H03K17/16

Abstract: First driver branch contains input stage (15) which connects, in response to first binary value of binary signal (Vx) applied to input node (X), output node (Y) to first logic potential (H) via first ohmic resistor (17). Second branch contains output stage (25) responsive to second binary value of binary signal applied to input node.Connection is effected via second ohmic resistor (27) with second logic potential (L). Duty cycle control (11,21) adjust signal travel time from input to output stage of first branch, relative to signal travel time from input to output of second branch.

公开(公告)号：DE10131708B4

公开(公告)日：2007-02-22

申请号：DE10131708

申请日：2001-06-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RUCKERBAUER HERMANN ,  SCHAEFER ANDRE

IPC: G11C7/02 ,  G11C7/10 ,  G11C7/22

Abstract: An integrated circuit for receiving a clock signal is described and has a clock input and a receiver circuit. A clock signal can be applied to the clock input. A filter circuit is provided, whose input is connected to the clock input for the purpose of filtering out a frequency and/or a frequency range of the clock signal. An output of the filter circuit, which output produces the filtered clock signal, is connected to the receiver circuit for the purpose of transferring the filtered clock signal to the integrated circuit for processing.

公开(公告)号：DE102005013238A1

公开(公告)日：2006-09-28

申请号：DE102005013238

申请日：2005-03-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHAEFER ANDRE

IPC: G11C7/10 ,  G11C11/407

Abstract: The method involves transferring control information from a controller (2) to a RAM (1) through a data channel for adjusting the operating parameters (Pa,Pb,Pc) of the drivers (19) in the data interface of the RAM. The control information is sent with control bits in a sequence of n is greater than or equal to 2 data bits. Some of the control bits are provided with appropriate binary value that follow a data clock. The control bits are sent in appropriate sequence one at a time based on the m-width unit of the data bit, where m is greater than 1. An independent claim is included for the control information transfer device.

公开(公告)号：DE10244401A1

公开(公告)日：2004-04-01

申请号：DE10244401

申请日：2002-09-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHAEFER ANDRE ,  PFEIFFER JOHANN ,  SZCYPINSKI KAZIMIERZ

IPC: G11C7/22 ,  G11C11/4076

Abstract: A component, especially a DDR-semiconductor component i.e. a DDR-semiconductor memory component, has differential input-clock pulses (CLK, CLKt;/CLK,/CLKt) applied to the terminals. The component has in addition a first and second clock-pulse relaying device, in which the first device (51) is provided for relaying the differential input signals and the second device (50) for relaying a single-input (single-ended) clock-signal (CLK,CLKt).

公开(公告)号：DE10244400A1

公开(公告)日：2004-04-01

申请号：DE10244400

申请日：2002-09-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHAEFER ANDRE ,  PFEIFFER JOHANN ,  SZCZYPINSKI KASIMIERZ ,  SCHNABEL JOACHIM

IPC: G11C7/22 ,  G11C11/4076 ,  G11C11/4063

Abstract: A circuit arrangement (1) having at least one terminal (3b) to which a clock/data signal (/CLK,/CLKt) can be applied. The circuit arrangement in addition has a clock-signal-ascertaining-device (2) for ascertaining whether a clock signal (/CLK,/CLKt) is present at the terminal (3b). An Independent claim is included for a semiconductor component i.e. a DDR (double data rate) component, especially a memory component, such as a DRAM..

公开(公告)号：DE10131708A1

公开(公告)日：2003-01-16

申请号：DE10131708

申请日：2001-06-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RUCKERBAUER HERMANN ,  SCHAEFER ANDRE

IPC: G11C7/10 ,  G11C7/02

Abstract: An integrated circuit for receiving a clock signal is described and has a clock input and a receiver circuit. A clock signal can be applied to the clock input. A filter circuit is provided, whose input is connected to the clock input for the purpose of filtering out a frequency and/or a frequency range of the clock signal. An output of the filter circuit, which output produces the filtered clock signal, is connected to the receiver circuit for the purpose of transferring the filtered clock signal to the integrated circuit for processing.