公开(公告)号：JP2003185709A

公开(公告)日：2003-07-03

申请号：JP2002270707

申请日：2002-09-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FISCHER HELMUT ,  PFEIFFER JOHANN ,  SCHNABEL RAINER FLORIAN

IPC: G01R31/28 ,  G11C11/401 ,  G11C29/00 ,  G11C29/12 ,  G11C29/14 ,  H01L21/822 ,  H01L27/04

Abstract: PROBLEM TO BE SOLVED: To reduce an electric current consumption in an operation time of an electronic circuit caused by a test module for testing the electronic circuit. SOLUTION: The present invention relates to a method of reducing the electric current consumption in the electronic circuit. The electronic circuit has the at least one test module 30 provided for testing the electronic circuit, and connected to at least one wire 38, 40 and/or one terminal of the electronic circuit. One test control signal 34 is generated, the at least one test module 30 is electrically separated at least partially from the at least one wire 38, 40 and/or the at least one terminal in an operation mode of the electronic circuit, using the test control signal, and a switching current is evaded in the at least one test module. COPYRIGHT: (C)2003,JPO

公开(公告)号：DE102004006288A1

公开(公告)日：2005-09-08

申请号：DE102004006288

申请日：2004-02-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GRUBER ARNDT ,  PFEIFFER JOHANN ,  EGGERS GEORG ERHARD ,  SCHROEDER STEPHAN ,  PROELL MANFRED

IPC: G11C7/00 ,  G11C7/10 ,  G11C29/00 ,  G11C29/36 ,  G11C29/50

公开(公告)号：DE10241142A1

公开(公告)日：2004-03-25

申请号：DE10241142

申请日：2002-09-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ZUCKERSTAETTER ANDREA ,  PFEIFFER JOHANN

IPC: G11C7/10 ,  G11C7/00 ,  G11C11/407

Abstract: The memory device has at least two memory cell arrays (13a,13b,13c,13d) connected to respective array logic circuitry (19a,19b,19c,19d). Data terminals or interface circuits (18a,18b) connected to them are directly connected to the respective array logic circuit.

公开(公告)号：DE10232962A1

公开(公告)日：2004-02-19

申请号：DE10232962

申请日：2002-07-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PFEIFFER JOHANN ,  FISCHER HELMUT

IPC: G11C11/408 ,  G11C11/4097 ,  G11C8/14 ,  G11C8/12 ,  G11C7/10

Abstract: A method for writing and reading data is performed on a dynamic memory circuit. The memory circuit has memory cells that can be addressed via word lines and bit lines. A word line is activated in the event of addressing of a memory area with a specific address. A word line has a plurality of mutually separate word line sections. Via the bit lines, in the event of addressing with the specific address, in parallel, a first number of data can be written to memory cells addressed by the address or the first number of data can be read from memory cells addressed by the address. In the event of addressing with a specific address, only a portion of the word line sections are activated, in order that only a portion of the memory cells connected to the word line are written to in parallel or read from in parallel.

公开(公告)号：DE10149099A1

公开(公告)日：2003-04-24

申请号：DE10149099

申请日：2001-10-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PFEIFFER JOHANN ,  FISCHER HELMUT

IPC: G11C7/12 ,  G11C7/18 ,  G11C11/4094 ,  G11C11/4097

Abstract: Each line circuit breaker (LS) has switching devices for sensing electrical potential in a pair of wires in each of the two-wire local and master data lines (LD,MD). The line circuit breaker transfers the logic potential to associated one of the pair of wires in master and local data lines, when one of the wires in the local and master data lines is at the logic potential, respectively.

公开(公告)号：DE10143033A1

公开(公告)日：2003-04-03

申请号：DE10143033

申请日：2001-09-01

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PFEIFFER JOHANN ,  FISCHER HELMUT ,  KLEHN BERND

IPC: G11C11/4076 ,  G11C11/4097 ,  G11C11/407 ,  G11C7/22

公开(公告)号：DE10104701A1

公开(公告)日：2002-08-29

申请号：DE10104701

申请日：2001-02-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SAVIGNAC DOMINIQUE ,  SCHNEIDER HELMUT ,  PFEFFERL PETER ,  PFEIFFER JOHANN

IPC: G11C7/18 ,  G11C11/4096 ,  G11C7/14

Abstract: The method involves writing data into the memory simultaneously over the adjacent pairs of data lines. When reading data, data are only read from one of the pairs of data lines. Each data line is connected to a bit line via a switch and the switches to the four data lines are closed before writing data. Independent claims are also included for the following: a memory arrangement with at least two pairs of data lines.

公开(公告)号：DE10226485A1

公开(公告)日：2005-06-23

申请号：DE10226485

申请日：2002-06-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PFEIFFER JOHANN ,  FISCHER HELMUT

IPC: G11C11/408 ,  G11C8/12

Abstract: A semiconductor memory includes: at least two memory banks that each have a memory cell matrix, an address decoding unit which includes a bank address decoding unit, a row address decoding unit and a column address decoding unit. At least one demultiplexer is connected upstream of the address buffer memories provided in the row address decoding unit and/or in the column address decoding unit. This demultiplexer is connected to the bank address decoder in order, on the basis of the decoded bank address, to activate the corresponding address buffer memory.

公开(公告)号：DE10232962B4

公开(公告)日：2004-07-08

申请号：DE10232962

申请日：2002-07-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PFEIFFER JOHANN ,  FISCHER HELMUT

IPC: G11C11/408 ,  G11C11/4097 ,  G11C8/14 ,  G11C8/12 ,  G11C7/10

Abstract: A method for writing and reading data is performed on a dynamic memory circuit. The memory circuit has memory cells that can be addressed via word lines and bit lines. A word line is activated in the event of addressing of a memory area with a specific address. A word line has a plurality of mutually separate word line sections. Via the bit lines, in the event of addressing with the specific address, in parallel, a first number of data can be written to memory cells addressed by the address or the first number of data can be read from memory cells addressed by the address. In the event of addressing with a specific address, only a portion of the word line sections are activated, in order that only a portion of the memory cells connected to the word line are written to in parallel or read from in parallel.

公开(公告)号：DE10224255B4

公开(公告)日：2004-05-06

申请号：DE10224255

申请日：2002-05-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PFEIFFER JOHANN ,  FISCHER HELMUT

IPC: G11C29/26 ,  G11C29/00

Abstract: A memory module has a memory cell configuration. For the purpose of testing the memory cell configuration, the memory module has a test structure with at least two test circuits, which are disposed in a distributed fashion on the memory module and are connected to one another via a common test switching bus, which can be connected to an address bus of the memory module via a decoupling circuit during a test operation.