公开(公告)号：DE10113821C2

公开(公告)日：2003-02-06

申请号：DE10113821

申请日：2001-03-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HEMMERT HEINRICH GEORG ,  KAISER ROBERT ,  SCHAMBERGER FLORIAN

IPC: G06F9/38 ,  G11C7/10 ,  G11C27/02 ,  G11C11/41

公开(公告)号：DE10119142A1

公开(公告)日：2002-10-31

申请号：DE10119142

申请日：2001-04-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KAISER ROBERT ,  SCHAMBERGER FLORIAN

IPC: G11C29/00

Abstract: A method for detecting and repairing erroneous addresses in semiconductor modules, in which faulty addresses are recognized by a test procedure and temporarily stored in latches and then stored in electrical fuses by finally applying an increased lead voltage. The lead voltage is only applied when at the end of the test procedure, at least one faulty address is temporarily stored in the latches.

公开(公告)号：DE10117614A1

公开(公告)日：2002-10-17

申请号：DE10117614

申请日：2001-04-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KAISER ROBERT ,  SCHAMBERGER FLORIAN ,  SCHNEIDER HELMUT

IPC: G11C11/401 ,  G11C7/10 ,  G11C7/22 ,  G11C11/407

Abstract: A method for operating a semiconductor memory at a data transmission rate which is twice as fast. According to the invention, data read access and data write access is divided up into two memories. A first memory bank is operated at one speed which is offset by a factor of 0.5 in relation to the operating speed of the second memory bank and the data partial flows are combined at the output of the two memory banks to form a data flow at a frequency which is multiplied by two.

公开(公告)号：DE10114443A1

公开(公告)日：2002-09-26

申请号：DE10114443

申请日：2001-03-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KAISER ROBERT ,  SCHAMBERGER FLORIAN ,  SCHNEIDER HELMUT

IPC: G11C7/10 ,  G11C8/04 ,  G11C7/00

Abstract: The method involves writing a data item into a memory cell selected by an address decoder, whereby the address is fed to the address decoder and the data item to the memory. The address is fed in earlier than the data item and is temporarily stored, then passed to the address decoder following a delay. The address and data item are almost simultaneously fed to the address decoder or amplifier circuit. AN Independent claim is also included for the following: a memory arrangement.

公开(公告)号：DE10113821A1

公开(公告)日：2002-09-26

申请号：DE10113821

申请日：2001-03-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HEMMERT HEINRICH GEORG ,  KAISER ROBERT ,  SCHAMBERGER FLORIAN

IPC: G06F9/38 ,  G11C7/10 ,  G11C27/02 ,  G11C11/41

Abstract: The device has several signal paths carrying external signals and each with a setup and hold circuit (12,16-19) based on a latch circuit with a full latch and a logic circuit (14). The latch circuit contains a hold latch (12) for early latching of the external signal and for decoupling the hold time from the startup time. The full latch (16-19) is arranged after the logic circuit to finally latch the external signal or a signal derived from it.

公开(公告)号：DE10063627A1

公开(公告)日：2002-07-18

申请号：DE10063627

申请日：2000-12-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KAISER ROBERT ,  SCHAMBERGER FLORIAN

IPC: G11C29/00

公开(公告)号：DE10026276A1

公开(公告)日：2001-12-13

申请号：DE10026276

申请日：2000-05-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KAISER ROBERT ,  LINDOLF JUERGEN ,  SCHNEIDER HELMUT ,  SCHAMBERGER FLORIAN ,  SCHAFFROTH THILO

IPC: G11C17/18 ,  G11C16/02 ,  G11C17/16 ,  G11C29/00

Abstract: The explicit high voltage source (1) and internal low voltage source (2) are selectively connected to respective connection areas (4,5) of a programmable fuse (3) by respective connectors (6,7). The switches (8,9) connect the connectors to the connection areas, when a control signal is applied to the switches from a controller (16), to apply required voltage.

公开(公告)号：DE10260818B4

公开(公告)日：2015-07-23

申请号：DE10260818

申请日：2002-12-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHAMBERGER FLORIAN ,  PETER JÖRG

IPC: H01L23/525 ,  H01C17/26 ,  H01L21/02 ,  H01L27/08

Abstract: Verfahren zum Einstellen eines Widerstandes in einer integrierten Schaltung, wobei der Widerstand einen ersten leitenden Bereich (1) und einen zweiten leitenden Bereich (3) aufweist, zwischen denen ein Widerstandsbereich (2) angeordnet ist, wobei ein Programmierstrom durch den Widerstand geleitet wird, wobei der Programmierstrom so gewählt wird, um in dem Widerstandsbereich einen Widerstandswert einzustellen, dadurch gekennzeichnet, dass der Widerstandsbereich (2) eine dielektrischen Schicht aufweist, wobei der Programmierstrom in den Widerstand so eingeprägt wird, dass eine Durchbruchspannung über der dielektrischen Schicht überschritten wird und sich ein oder mehrere Durchbruchskanäle ausbilden, wobei der Widerstandeswertes abhängig von der Größe des einen Durchbruchskanals oder der mehreren Durchbruchskanäle ist.

公开(公告)号：DE19835258B4

公开(公告)日：2006-07-27

申请号：DE19835258

申请日：1998-08-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KAISER ROBERT ,  KRASSER HANS-JUERGEN ,  SCHAMBERGER FLORIAN

IPC: G06F11/27 ,  G11C29/00 ,  G11C29/14 ,  G11C29/18

Abstract: An integrated circuit incorporating a self-test device and a method for producing a self-testing integrated circuit. The integrated circuit has a program memory with at least one external terminal for loading external test programs. The integrated circuit has a self-test device connected to the program memory, the self-test device executing program commands of a test program loaded into the program memory, the program commands succeeding one another in address terms, for carrying out a self-test of the circuit. The self-test device has an interrupt signal input, through which the self-test device interrupts the test program that is currently being executed by not executing the respective succeeding program command in address terms. Rather, it executes a program jump within the test program, the program jump being triggered by the interrupt signal.

公开(公告)号：DE50107003D1

公开(公告)日：2005-09-08

申请号：DE50107003

申请日：2001-12-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KAISER ROBERT ,  SCHAMBERGER FLORIAN

IPC: G11C17/16 ,  G11C17/18 ,  G11C29/00

Abstract: A circuit configuration for driving a programmable link has a volatile memory cell, which is coupled to the fuse for the permanent storage of data stored in the volatile memory, and also a shift register, which enables data to be read out from the volatile memory cell and data to be written to the memory cell. In this case, a plurality of shift registers may be interconnected to form a shift register chain for the purpose of driving a plurality of fuses. The shift register chain thus enables fast writing and reading to/from the volatile memory with a low outlay on circuitry.