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公开(公告)号：GB2291513B
公开(公告)日：1999-04-28
申请号：GB9414028
申请日：1994-07-12
Applicant: INTEL CORP
Inventor： HOYT BRADLEY D , HINTON GLENN J , GLEW ANDREW F , NATARAJAN SUBRAMANIAN
IPC: G06F9/38
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32.发明专利
公开(公告)号：SG52391A1
公开(公告)日：1998-09-28
申请号：SG1996003892
申请日：1994-10-21
Applicant: INTEL CORP
Inventor： HOYT BRADLEY D , HINTON GLENN J , PAPWORTH DAVID B , GUPTA ASHWANI KUMAR , FETTERMAN MICHAEL ALAN , NATARAJAN SUBRAMANIAN , SHENOY SUNIL , D´SA REYNOLD V
IPC: G06F9/38
Abstract: A four stage branch instruction resolution system for a pipelined processor is disclosed. A first stage of the branch instruction resolution system predicts the existence and outcome of branch instructions within an instruction stream such that an instruction fetch unit can continually fetch instructions. A second stage decodes all the instructions fetched. If the decode stage determines that a branch instruction predicted by the first stage is not a branch instruction, the decode stage flushes the pipeline and restarts the processor at a corrected address. The decode stage verifies all branch predictions made by the branch prediction stage. Finally, the decode stage makes branch predictions for branches not predicted by the branch prediction stage. A third stage executes all the branch instructions to determine a final branch outcome and a final branch target address. The branch execution stage compares the final branch outcome and final branch target address with the predicted branch outcome and predicted branch target address to determine if the processor must flush the front-end of the microprocessor pipeline and restart at a corrected address. A final branch resolution stage retires all branch instructions. The retirement stage ensures that any instructions fetched after a mispredicted branch are not committed into permanent state.
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公开(公告)号：SG50458A1
公开(公告)日：1998-07-20
申请号：SG1996001871
申请日：1994-08-11
Applicant: INTEL CORP
Inventor： BRAYTON JAMES M , RHODEHAMEL MICHAEL W , SARANGDHAR NITIN V , HINTON GLENN J
Abstract: A computer system, and a method performed by it, having a mechanism for ensuring consistency of data among various level(s) of caching in a multi-level hierarchical memory system. The cache consistency mechanism includes an external bus request queue which and associated mechanism, which cooperate to monitor and control the issuance of data requests, such as read requests and write requests, onto an external bus. The computer system includes one or more CPUs each having this consistency mechanism.
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公开(公告)号：SE9503951D0
公开(公告)日：1995-11-08
申请号：SE9503951
申请日：1995-11-08
Applicant: INTEL CORP
Inventor： HOYT BRADLEY D , HINTON GLENN J , GLEW ANDREW F , NATARAJAN SUBRAMANIAN
Abstract: The branch prediction appts maintains both speculative history (25) and actual history (22) for each branch instruction in a branch target buffer. The actual branch history contains the branch history for fully resolved occurrences of the branch instruction. The speculative branch history contains the actual history and in addition the history of recent branch predictions. If the speculative branch history contains any recent predictions, then a speculation bit (24) is set. When the speculative bit is set, this indicates that there is a speculative history for a branch. Therefore, when the speculation bit is set the speculative history is used to make branch predictions. If a mis-prediction is made for the branch, the speculative bit is cleared since the speculative history contains inaccurate branch history.
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公开(公告)号：DE19506734A1
公开(公告)日：1995-09-07
申请号：DE19506734
申请日：1995-02-27
Applicant: INTEL CORP
Inventor： BRAYTON JAMES M , RHODEHAMEL MICHAEL W , SARANGDHAR NITIN V , HINTON GLENN J
IPC: G06F9/38 , G06F12/08 , G06F13/18 , G06F13/16 , G06F15/167
Abstract: A computer system, and a method performed by it, having a mechanism for ensuring consistency of data among various level(s) of caching in a multi-level hierarchical memory system. The cache consistency mechanism includes an external bus request queue which and associated mechanism, which cooperate to monitor and control the issuance of data requests, such as read requests and write requests, onto an external bus. The computer system includes one or more CPUs each having this consistency mechanism.
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Patent Agency Ranking
公开(公告)号：PL307460A1
公开(公告)日：1995-09-04
申请号：PL30746095
申请日：1995-02-27
Applicant: INTEL CORP
Inventor： HINTON GLENN J , PAPWORTH DAVID B , GLEW ANDREW F , FETTERMAN MICHAEL A , COLWELL ROBERT P
Abstract: A pipelined method for executing instructions in a computer system. The present invention includes providing multiple instructions as a continuous stream of operations. This stream of operations is provided in program order. In one embodiment, the stream of operations is provided by performing an instruction cache memory lookup to fetch the multiple instructions, performing instruction length decoding on the instructions, rotating the instructions, and decoding the instructions. The present invention also performs register renaming, allocates resources and sends a portion of each of the operations to a buffering mechanism (e.g., a reservation station). The instruction cache memory lookup, instruction length decoding, rotation and decoding of the instructions, as well as the register renaming, are performed in consecutive pipestages. The present invention provides for executing the instructions in an out-of-order pipeline. The execution produces results. In one embodiment, the instructions are executed by determining the data readiness of each of the operations and scheduling data ready operations. These scheduled data ready operations are dispatched to an execution unit and executed. The results are written back for use by other operations or as data output or indication. The determination of execution readiness, the dispatching and the execution, and writeback, are performed in consecutive pipestages. The present invention also provides for retiring each of the continuous stream of operations in such a manner as to commit their results to architectural state and to reestablish sequential program order.
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公开(公告)号：DE112011105984T5
公开(公告)日：2014-09-18
申请号：DE112011105984
申请日：2011-12-20
Applicant: INTEL CORP
Inventor： RAMANUJAN RAJ K , HINTON GLENN J , ZIMMERMAN DAVID J
IPC: G06F12/08
Abstract: Es werden ein System und ein Verfahren zum Entleeren eines vorgegebenen Bereichs eines arbeitsspeicherseitigen Zwischenspeichers (MSC) in einer Arbeitsspeicherhierarchie auf mehreren Ebenen beschrieben. Beispielsweise umfasst ein Computersystem nach einer Ausführungsform: ein Arbeitsspeicher-Teilsystem, das aus einem nicht flüchtigen Systemspeicher und einem flüchtigen arbeitsspeicherseitigen Zwischenspeicher (MSC) zum Zwischenspeichern von Teilen des nicht flüchtigen Systemspeichers besteht; und eine Entleerungs-Engine zum Entleeren eines vorgegebenen Bereichs des MSC in den nicht flüchtigen Systemspeicher als Reaktion auf einen Deaktivierungszustand, der mit dem vorgegebenen Bereich des MSC verknüpft ist.
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公开(公告)号：DE102014003855A1
公开(公告)日：2014-09-18
申请号：DE102014003855
申请日：2014-03-17
Applicant: INTEL CORP
Inventor： MUTHIAH BHARATH , RASH WILLIAM BILL , HINTON GLENN J , DIXON MARTIN G , HAHN SCOTT D , PAPWORTH DAVID B
IPC: H04N21/2343
Abstract: In einer Ausführungsform wird eine auf Quality-of-Service(QoS)-Kriterien basierende serverseitige Binärübersetzung und Ausführung von Anwendungen auf mehreren Servern unter Verwendung einer verteilten Übersetzung und Ausführung entweder in einer virtualisierten oder nativen Ausführungsumgebung durchgeführt. Die übersetzten Anwendungen werden ausgeführt, um Ausgabeanzeigedaten zu erzeugen, die Ausgabeanzeigedaten werden in ein Medienformat codiert, und der Videostrom wird über ein Netzwerk einer Client-Vorrichtung zugeführt. In einer Ausführungsform unterstützen ein oder mehrere Grafikprozessoren die Hauptprozessoren der Server durch Beschleunigung des Renderns der Anwendungsausgabe, und ein Medienencoder codiert die Anwendungsausgabe in ein Medienformat.
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公开(公告)号：GB2376328A
公开(公告)日：2002-12-11
申请号：GB0221325
申请日：2000-12-29
Applicant: INTEL CORP
Inventor： UPTON MICHAEL D , SAGER DAVID J , BOGGS DARRELL D , HINTON GLENN J
Abstract: According to one aspect of the invention, a microprocessor is provided that includes an execution core, a first replay mechanism and a second replay mechanism. The execution core performs data speculation in executing a first instruction. The first replay mechanism is used to replay the first instruction via a first replay path if an error of a first type is detected which indicates that the data speculation is erroneous. The second replay mechanism is used to replay the first instruction via a second replay path if an error of a second type is detected which indicates that the data speculation is erroneous.
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公开(公告)号：SE515698C2
公开(公告)日：2001-09-24
申请号：SE9503951
申请日：1995-11-08
Applicant: INTEL CORP
Inventor： HOYT BRADLEY D , HINTON GLENN J , GLEW ANDREW F , NATARAJAN SUBRAMANIAN
Abstract: The branch prediction appts maintains both speculative history (25) and actual history (22) for each branch instruction in a branch target buffer. The actual branch history contains the branch history for fully resolved occurrences of the branch instruction. The speculative branch history contains the actual history and in addition the history of recent branch predictions. If the speculative branch history contains any recent predictions, then a speculation bit (24) is set. When the speculative bit is set, this indicates that there is a speculative history for a branch. Therefore, when the speculation bit is set the speculative history is used to make branch predictions. If a mis-prediction is made for the branch, the speculative bit is cleared since the speculative history contains inaccurate branch history.
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