公开(公告)号：US20240203806A1

公开(公告)日：2024-06-20

申请号：US18085291

申请日：2022-12-20

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Bai Nie ,  Leonel R. Arana ,  Dingying XU ,  Srinivas Venkata Ramanuja Pietambaram ,  Hongxia Feng ,  Gang Duan ,  Xiaoying Guo ,  Jeremy D. Ecton ,  Haobo Chen ,  Bin Mu

IPC: H01L23/15 ,  C03C17/00 ,  C03C17/06 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/15 ,  C03C17/004 ,  C03C17/06 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  C03C2217/253 ,  C03C2218/365

Abstract: An electronic device, including layers, formed from a material that can remain substantially constant in structure, such as glass. The layer can be preformed with through glass vias that support at least one electrically conductive interconnect. The through glass via can have an edge region that can be substantially coplanar with an exposed surface of the layer.

公开(公告)号：US11676891B2

公开(公告)日：2023-06-13

申请号：US17364686

申请日：2021-06-30

Applicant: Intel Corporation

Inventor： Hongxia Feng ,  Dingying David Xu ,  Sheng C. Li ,  Matthew L. Tingey ,  Meizi Jiao ,  Chung Kwang Christopher Tan

IPC: H01L23/498 ,  H01L23/13 ,  H01L21/48 ,  H01L23/538

CPC classification number: H01L23/49838 ,  H01L21/486 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/49866 ,  H01L23/5385 ,  H01L23/49816 ,  H01L23/5383 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: A package substrate and package assembly including a package substrate including a substrate body including electrical routing features therein and a surface layer and a plurality of first and second contact points on the surface layer including a first pitch and a second pitch, respectively, wherein the plurality of first contact points and the plurality of second contact points are continuous posts to the respective ones of the electrical routing features. A method including forming first conductive vias in a package assembly, wherein the first conductive vias include substrate conductive vias to electrical routing features in a package substrate and bridge conductive vias to bridge surface routing features of a bridge substrate; forming a first surface layer and a second surface layer on the package substrate; and forming second conductive vias through each of the first surface layer and the second surface layer to the bridge conductive vias.

公开(公告)号：US20230022714A1

公开(公告)日：2023-01-26

申请号：US17956769

申请日：2022-09-29

Applicant: Intel Corporation

Inventor： Hongxia Feng ,  Dungying David Xu ,  Sheng C. Li ,  Matthew L. Tingey ,  Meizi Jiao ,  Chung Kwang Christopher Tan

IPC: H01L23/498 ,  H01L23/13 ,  H01L21/48 ,  H01L23/538

Abstract: A package substrate and package assembly including a package substrate including a substrate body including electrical routing features therein and a surface layer and a plurality of first and second contact points on the surface layer including a first pitch and a second pitch, respectively, wherein the plurality of first contact points and the plurality of second contact points are continuous posts to the respective ones of the electrical routing features. A method including forming first conductive vias in a package assembly, wherein the first conductive vias include substrate conductive vias to electrical routing features in a package substrate and bridge conductive vias to bridge surface routing features of a bridge substrate; forming a first surface layer and a second surface layer on the package substrate; and forming second conductive vias through each of the first surface layer and the second surface layer to the bridge conductive vias.

公开(公告)号：US12033930B2

公开(公告)日：2024-07-09

申请号：US17033392

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Jieying Kong ,  Yiyang Zhou ,  Suddhasattwa Nad ,  Jeremy Ecton ,  Hongxia Feng ,  Tarek Ibrahim ,  Brandon Marin ,  Zhiguo Qian ,  Sarah Blythe ,  Bohan Shan ,  Jason Steill ,  Sri Chaitra Jyotsna Chavali ,  Leonel Arana ,  Dingying Xu ,  Marcel Wall

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L21/485 ,  H01L23/49827

Abstract: An integrated circuit (IC) package substrate, comprising a metallization level within a dielectric material. The metallization level comprises a plurality of conductive features, each having a top surface and a sidewall surface. The top surface of a first conductive feature of the plurality of conductive features has a first average surface roughness, and the sidewall surface of a second conductive feature of the plurality of conductive features has a second average surface roughness that is less than the first average surface roughness.

公开(公告)号：US20240222345A1

公开(公告)日：2024-07-04

申请号：US18090707

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Haobo Chen ,  Bai Nie ,  Srinivas Pietambaram ,  Gang Duan ,  Kyle Arrington ,  Ziyin Lin ,  Hongxia Feng ,  Yiqun Bai ,  Xiaoying Guo ,  Dingying Xu ,  Kristof Darmawikarta

IPC: H01L25/18 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/15 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00

CPC classification number: H01L25/18 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/56 ,  H01L23/15 ,  H01L23/3121 ,  H01L23/5383 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/05647 ,  H01L2224/08225 ,  H01L2224/80447 ,  H01L2224/80895

Abstract: An apparatus is provided which comprises: a plurality of interconnect layers within a substrate, a layer of organic dielectric material over the plurality of interconnect layers, copper pads within the layer of organic dielectric material, a first integrated circuit device copper-to-copper bonded with the copper pads, inorganic dielectric material over the layer of organic dielectric material, the inorganic dielectric material embedding the first integrated circuit device, and the inorganic dielectric material extending across a width of the substrate, and a second integrated circuit device coupled with a substrate surface above the inorganic dielectric material. Other embodiments are also disclosed and claimed.

公开(公告)号：US20240222301A1

公开(公告)日：2024-07-04

申请号：US18147497

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Hongxia Feng ,  Haobo Chen ,  Srinivas Pietambaram ,  Bai Nie ,  Gang Duan ,  Kyle Arrington ,  Ziyin Lin ,  Yiqun Bai ,  Xiaoying Guo ,  Dingying Xu ,  Sairam Agraharam ,  Ashay Dani ,  Eric J. M. Moret ,  Tarek Ibrahim

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L2224/10122 ,  H01L2224/11011 ,  H01L2924/143 ,  H01L2924/186

Abstract: Methods and apparatus for optical thermal treatment in semiconductor packages are disclosed. A disclosed example integrated circuit (IC) package includes a dielectric substrate, an interconnect associated with the dielectric substrate, and light absorption material proximate or surrounding the interconnect, the light absorption material to increase in temperature in response to being exposed to a pulsed light for thermal treatment corresponding to the IC package.

公开(公告)号：US20240222283A1

公开(公告)日：2024-07-04

申请号：US18147487

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Hongxia Feng ,  Bohan Shan ,  Bai Nie ,  Xiaoxuan Sun ,  Holly Sawyer ,  Tarek Ibrahim ,  Adwait Telang ,  Dingying Xu ,  Leonel Arana ,  Xiaoying Guo ,  Ashay Dani ,  Sairam Agraharam ,  Haobo Chen ,  Srinivas Pietambaram ,  Gang Duan

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/5386 ,  H01L23/49816 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2924/15311

Abstract: Methods and apparatus to prevent over-etch in semiconductor packages are disclosed. A disclosed example semiconductor package includes at least one dielectric layer, an interconnect extending at least partially through or from the at least one dielectric layer, and a material on at least a portion of the interconnect, wherein the material comprises at least one of silicon or titanium.

公开(公告)号：US20240222259A1

公开(公告)日：2024-07-04

申请号：US18147535

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Haobo Chen ,  Bohan Shan ,  Xiyu Hu ,  Rhonda Jack ,  Catherine Mau ,  Hongxia Feng ,  Xiao Liu ,  Wei Wei ,  Srinivas Pietambaram ,  Gang Duan ,  Xiaoying Guo ,  Dingying Xu ,  Kyle Arrington ,  Ziyin Lin ,  Hiroki Tanaka ,  Leonel Arana

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/29 ,  H01L23/31

CPC classification number: H01L23/49894 ,  H01L21/481 ,  H01L23/291 ,  H01L23/3192 ,  H01L24/16

Abstract: Methods, systems, apparatus, and articles of manufacture to produce integrated circuit (IC) packages having silicon nitride adhesion promoters are disclosed. An example IC package disclosed herein includes a metal layer on a substrate, a layer on the metal layer, the layer including silicon and nitrogen, and solder resist on the layer.

公开(公告)号：US20240222136A1

公开(公告)日：2024-07-04

申请号：US18091188

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Haobo Chen ,  Srinivas Venkata Ramanuja Pietambaram ,  Hongxia Feng ,  Gang Duan ,  Xiaoying Guo ,  Ashay A. Dani ,  Yiqun Bai ,  Dingying Xu ,  Bai Nie ,  Kyle Jordan Arrington ,  Wei Wei ,  Ziyin Lin

IPC: H01L21/321 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L21/3212 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/76814 ,  H01L21/7684

Abstract: Mechanical or chemical processes can form roughened surfaces which can be used for coupling layers of electrical systems such as when forming dies, substrates, computer chips or the like that, when subjected to high stress, are robust enough to remain coupled together.

公开(公告)号：US20240203853A1

公开(公告)日：2024-06-20

申请号：US18085281

申请日：2022-12-20

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Haobo Chen ,  Hongxia Feng ,  Julianne Troiano ,  Dingying Xu ,  Matthew Tingey ,  Xiaoying Guo ,  Srinivas Venkata Ramanuja Pietambaram ,  Bai Nie ,  Gang Duan ,  Bin Mu ,  Kyle Mcelhinny ,  Ashay A. Dani ,  Leonel R. Arana

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/538

CPC classification number: H01L23/49827 ,  H01L21/4846 ,  H01L23/5384

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device can include a substrate, a via, a build-up layer, a top layer, and one or more dies. The substrate can include a conductor coating. The via can be connected to the conductor coating. The build-up layer can be on the substrate. The build-up layer can define a channel that the via is formed within and insulate the via during operation of the electronic device. The top layer can be interproximal to the substrate and the via. The one or more dies can be connected to the via.